litex/misoclib/mem/litesata/doc/source/docs/simulation/index.rst

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.. _simulation-index:
==========
Simulation
==========
.. note::
Please contribute to this document, or support us financially to write it.
Simulations are available in ./test:
- :code:`crc_tb`
- :code:`scrambler_tb`
- :code:`phy_datapath_tb`
- :code:`link_tb`
- :code:`command_tb`
- :code:`bist_tb`
- :code:`striping_tb`
- :code:`mirroring_tb`
Models for all the layers of SATA and a simplified HDD model are provided.
To run a simulation, go to ./test and run:
- :code:`make <simulation_name>`