Olof Kindgren ffb6081720 litesata/example_designs: Add missing clock in phy instantiation		2015-06-26 01:20:25 +02:00
..
__init__.py	liteXXX cores: remove Identifier duplication	2015-03-01 11:24:58 +01:00
bist.py	litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)	2015-06-10 12:15:59 +02:00
core.py	litesata/example_designs: Add missing clock in phy instantiation	2015-06-26 01:20:25 +02:00
mirroring.py	litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)	2015-06-10 12:15:59 +02:00
striping.py	litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)	2015-06-10 12:15:59 +02:00