2015-07-19 10:09:19 -04:00
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`timescale 1 ns / 1 ps
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module testbench;
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reg clk_pin = 1;
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always #5 clk_pin = ~clk_pin;
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wire LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7;
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top uut (
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.clk_pin(clk_pin),
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.LED0(LED0),
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.LED1(LED1),
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.LED2(LED2),
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.LED3(LED3),
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.LED4(LED4),
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.LED5(LED5),
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.LED6(LED6),
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.LED7(LED7)
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);
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initial begin
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if ($test$plusargs("vcd")) begin
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$dumpfile("example.vcd");
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$dumpvars(0, testbench);
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end
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$monitor(LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0);
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2015-07-21 11:43:33 -04:00
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repeat (10000) @(posedge clk_pin);
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2015-07-19 10:09:19 -04:00
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$finish;
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end
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endmodule
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