mirror of https://github.com/YosysHQ/picorv32.git
91 lines
3.3 KiB
ArmAsm
91 lines
3.3 KiB
ArmAsm
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# See LICENSE for license details.
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#*****************************************************************************
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# sra.S
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#-----------------------------------------------------------------------------
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#
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# Test sra instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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TEST_RR_OP( 2, sra, 0x80000000, 0x80000000, 0 );
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TEST_RR_OP( 3, sra, 0xc0000000, 0x80000000, 1 );
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TEST_RR_OP( 4, sra, 0xff000000, 0x80000000, 7 );
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TEST_RR_OP( 5, sra, 0xfffe0000, 0x80000000, 14 );
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TEST_RR_OP( 6, sra, 0xffffffff, 0x80000001, 31 );
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TEST_RR_OP( 7, sra, 0x7fffffff, 0x7fffffff, 0 );
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TEST_RR_OP( 8, sra, 0x3fffffff, 0x7fffffff, 1 );
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TEST_RR_OP( 9, sra, 0x00ffffff, 0x7fffffff, 7 );
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TEST_RR_OP( 10, sra, 0x0001ffff, 0x7fffffff, 14 );
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TEST_RR_OP( 11, sra, 0x00000000, 0x7fffffff, 31 );
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TEST_RR_OP( 12, sra, 0x81818181, 0x81818181, 0 );
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TEST_RR_OP( 13, sra, 0xc0c0c0c0, 0x81818181, 1 );
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TEST_RR_OP( 14, sra, 0xff030303, 0x81818181, 7 );
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TEST_RR_OP( 15, sra, 0xfffe0606, 0x81818181, 14 );
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TEST_RR_OP( 16, sra, 0xffffffff, 0x81818181, 31 );
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# Verify that shifts only use bottom five bits
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TEST_RR_OP( 17, sra, 0x81818181, 0x81818181, 0xffffffc0 );
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TEST_RR_OP( 18, sra, 0xc0c0c0c0, 0x81818181, 0xffffffc1 );
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TEST_RR_OP( 19, sra, 0xff030303, 0x81818181, 0xffffffc7 );
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TEST_RR_OP( 20, sra, 0xfffe0606, 0x81818181, 0xffffffce );
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TEST_RR_OP( 21, sra, 0xffffffff, 0x81818181, 0xffffffff );
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#-------------------------------------------------------------
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# Source/Destination tests
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#-------------------------------------------------------------
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TEST_RR_SRC1_EQ_DEST( 22, sra, 0xff000000, 0x80000000, 7 );
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TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffe0000, 0x80000000, 14 );
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TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 );
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_RR_DEST_BYPASS( 25, 0, sra, 0xff000000, 0x80000000, 7 );
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TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffe0000, 0x80000000, 14 );
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TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffff, 0x80000000, 31 );
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TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xff000000, 0x80000000, 7 );
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TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffe0000, 0x80000000, 14 );
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TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffff, 0x80000000, 31 );
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TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xff000000, 0x80000000, 7 );
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TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffe0000, 0x80000000, 14 );
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TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffff, 0x80000000, 31 );
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TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xff000000, 0x80000000, 7 );
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TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffe0000, 0x80000000, 14 );
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TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffff, 0x80000000, 31 );
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TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xff000000, 0x80000000, 7 );
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TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffe0000, 0x80000000, 14 );
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TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffff, 0x80000000, 31 );
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TEST_RR_ZEROSRC1( 40, sra, 0, 15 );
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TEST_RR_ZEROSRC2( 41, sra, 32, 32 );
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TEST_RR_ZEROSRC12( 42, sra, 0 );
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TEST_RR_ZERODEST( 43, sra, 1024, 2048 );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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