1
0
Fork 0
mirror of https://github.com/YosysHQ/picorv32.git synced 2025-01-03 03:43:38 -05:00
picorv32/scripts/yosys/synth_sim.ys

8 lines
211 B
Text
Raw Normal View History

2015-06-29 19:46:25 -04:00
# yosys synthesis script for post-synthesis simulation (make test_synth)
read_verilog picorv32.v
chparam -set ENABLE_IRQ 1 -set ENABLE_MUL 1 picorv32_axi
hierarchy -top picorv32_axi
synth
write_verilog synth.v