mirror of https://github.com/YosysHQ/picorv32.git
8 lines
211 B
Plaintext
8 lines
211 B
Plaintext
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# yosys synthesis script for post-synthesis simulation (make test_synth)
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read_verilog picorv32.v
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chparam -set ENABLE_IRQ 1 -set ENABLE_MUL 1 picorv32_axi
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hierarchy -top picorv32_axi
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synth
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write_verilog synth.v
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