mirror of https://github.com/YosysHQ/picorv32.git
59 lines
1.4 KiB
Coq
59 lines
1.4 KiB
Coq
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`timescale 1 ns / 1 ps
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module test_soc (
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input clk,
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input resetn,
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output trap,
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output [7:0] out_byte,
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output out_byte_en,
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output monitor_valid,
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output [31:0] monitor_addr,
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output [31:0] monitor_data
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);
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parameter MEM_SIZE = 64*1024/4;
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wire mem_valid;
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wire mem_instr;
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wire mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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wire [31:0] mem_rdata;
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picorv32 uut (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid(mem_valid),
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.mem_instr(mem_instr),
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.mem_ready(mem_ready),
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.mem_addr (mem_addr ),
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.mem_wdata(mem_wdata),
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.mem_wstrb(mem_wstrb),
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.mem_rdata(mem_rdata)
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);
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assign monitor_valid = mem_valid;
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assign monitor_addr = mem_addr;
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assign monitor_data = mem_wstrb ? mem_wdata : mem_rdata;
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reg [31:0] memory [0:MEM_SIZE-1];
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initial $readmemh("../firmware/firmware.hex", memory);
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assign mem_ready = 1;
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assign mem_rdata = memory[mem_addr >> 2];
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assign out_byte = mem_wdata[7:0];
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assign out_byte_en = mem_addr == 32'h1000_0000;
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always @(posedge clk) begin
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if (mem_valid && (mem_addr >> 2) < MEM_SIZE) begin
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if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
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end
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end
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endmodule
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