mirror of https://github.com/YosysHQ/picorv32.git
48 lines
2.0 KiB
Plaintext
48 lines
2.0 KiB
Plaintext
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Checking equivalence of different configurations of PicoRV32 using Yosys and
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SMT solvers (Yices, Z3, CVC4, MathSAT).
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The PicoRV32 core provides configuration parameters that change the supported
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ISA and/or the timing of the core. This set of scripts uses model checking
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techniques to proof equivalence of cores in different configurations, thus
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transfering the confidence in the cores gained by running test benches on a few
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configurations to the rest of the configurations.
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async
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-----
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The async test compares two cores with different timings (number of clock
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cycles per operation), but same ISA. The SMT problem models the following
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scenario:
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The cores start out with identical memory and register file. In cycle 0 the
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reset input is active, in all other cycles the reset input is inactive. The
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trap output must by active in the last cycle for both cores. I.e. whatever
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the program in memory does, it must terminate in a trap and it must do so
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for both cores within the simulated number of clock cycles.
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The script searches for a trace that ends in different memory content and/or
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different register file content in the last cycle, i.e. a trace that exposes
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divergent behavior in the two cores.
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sync
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----
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The sync test compares two cores same timings but different ISA. The ISA of the
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2nd code (main_b) must be a superset of the ISA of the first core (main_a), and
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catching illegal instructions and illegal memory transfers must be enabled in
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the first core. The SMT problem models the following scenario:
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The cores start out with identical memory and register file. In cycle 0 the
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reset input is active, in all other cycles the reset input is inactive. The
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cores are run in parallel for a number of cycles with the first core not going
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into the trap state. I.e. all traces are limited to the ISA supported by the
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first core.
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The script searches for a trace that ends in different memory content and/or
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different register file content in the last cycle, i.e. a trace that exposes
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divergent behavior in the two cores.
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