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spimemio documentation: read latency reset value 

According to c06ba38113/picosoc/spimemio.v (L111) the reset value for `Read latency (dummy) cycles` is 8 cycles, not 0.
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Maciej T. Nowak 2020-01-03 21:57:19 +01:00 committed by GitHub
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@ -75,7 +75,7 @@ mapped to the low byte of the 32 bit word at address 0x03000000.
| 22 | DDR Enable bit (reset=0) | | 22 | DDR Enable bit (reset=0) |
| 21 | QSPI Enable bit (reset=0) | | 21 | QSPI Enable bit (reset=0) |
| 20 | CRM Enable bit (reset=0) | | 20 | CRM Enable bit (reset=0) |
| 19:16 | Read latency (dummy) cycles (reset=0) | | 19:16 | Read latency (dummy) cycles (reset=8) |
| 15:12 | Reserved (read 0) | | 15:12 | Reserved (read 0) |
| 11:8 | IO Output enable bits in bit bang mode | | 11:8 | IO Output enable bits in bit bang mode |
| 7:6 | Reserved (read 0) | | 7:6 | Reserved (read 0) |