mirror of https://github.com/YosysHQ/picorv32.git
Added "make check"
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parent
6783abd994
commit
07f28068f6
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@ -20,6 +20,8 @@
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/testbench_synth.exe
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/testbench_synth.exe
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/testbench.gtkw
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/testbench.gtkw
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/testbench.vcd
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/testbench.vcd
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/check.smt2
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/check.vcd
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/synth.log
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/synth.log
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/synth.v
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/synth.v
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.*.swp
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.*.swp
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13
Makefile
13
Makefile
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@ -14,6 +14,15 @@ testbench.vcd: testbench.exe firmware/firmware.hex
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view: testbench.vcd
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view: testbench.vcd
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gtkwave $< testbench.gtkw
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gtkwave $< testbench.gtkw
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check: check.smt2
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# yosys-smtbmc -m picorv32 check.smt2
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yosys-smtbmc -m picorv32 -t 10 -c check.vcd -i check.smt2
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check.smt2: picorv32.v
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yosys -v2 -p 'read_verilog -formal picorv32.v' \
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-p 'prep -top picorv32 -nordff' \
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-p 'write_smt2 -bv -mem -wires check.smt2'
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test_sp: testbench_sp.exe firmware/firmware.hex
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test_sp: testbench_sp.exe firmware/firmware.hex
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vvp -N testbench_sp.exe
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vvp -N testbench_sp.exe
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@ -69,9 +78,9 @@ toc:
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gawk '/^-+$$/ { y=tolower(x); gsub("[^a-z0-9]+", "-", y); gsub("-$$", "", y); printf("- [%s](#%s)\n", x, y); } { x=$$0; }' README.md
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gawk '/^-+$$/ { y=tolower(x); gsub("[^a-z0-9]+", "-", y); gsub("-$$", "", y); printf("- [%s](#%s)\n", x, y); } { x=$$0; }' README.md
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clean:
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clean:
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rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) \
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rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) check.smt2 check.vcd synth.v synth.log \
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firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
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firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
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synth.v testbench.exe testbench_sp.exe testbench_axi.exe testbench_synth.exe testbench.vcd
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testbench.exe testbench_sp.exe testbench_axi.exe testbench_synth.exe testbench.vcd
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.PHONY: test view test_sp test_axi test_synth toc clean
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.PHONY: test view test_sp test_axi test_synth toc clean
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20
picorv32.v
20
picorv32.v
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@ -1092,6 +1092,26 @@ module picorv32 #(
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reg_next_pc[1:0] <= 0;
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reg_next_pc[1:0] <= 0;
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current_pc = 'bx;
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current_pc = 'bx;
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end
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end
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// Formal Verification
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`ifdef FORMAL
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reg [3:0] cycle = 0;
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always @(posedge clk) begin
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if (~&cycle)
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cycle <= cycle + 1;
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end
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always @* begin
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assume (resetn == |cycle);
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if (cycle) begin
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// instruction fetches are read-only
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if (mem_valid && mem_instr)
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assert (mem_wstrb == 0);
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end
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end
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`endif
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endmodule
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endmodule
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