mirror of https://github.com/YosysHQ/picorv32.git
Added mul/div support to scripts/torture/
This commit is contained in:
Clifford Wolf
parent
472dae6b43
commit
094783dcf8
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@ -54,7 +54,7 @@ tests/test_$(1).S: tests/generated.ok
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touch tests/test_$(1).S
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tests/test_$(1).elf: tests/test_$(1).S
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riscv32-unknown-elf-gcc -m32 -march=RV32IC -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -I. -o tests/test_$(1).elf tests/test_$(1).S
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riscv32-unknown-elf-gcc -m32 -march=RV32IMC -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -I. -o tests/test_$(1).elf tests/test_$(1).S
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tests/test_$(1).bin: tests/test_$(1).elf
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riscv32-unknown-elf-objcopy -O binary tests/test_$(1).elf tests/test_$(1).bin
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@ -1,5 +1,5 @@
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diff --git a/config/default.config b/config/default.config
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index b671223..e6bd131 100644
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index b671223..c0b2bb4 100644
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--- a/config/default.config
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+++ b/config/default.config
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@@ -1,18 +1,18 @@
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@ -7,11 +7,9 @@ index b671223..e6bd131 100644
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torture.generator.memsize 1024
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torture.generator.fprnd 0
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-torture.generator.amo true
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-torture.generator.mul true
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-torture.generator.divider true
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+torture.generator.amo false
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+torture.generator.mul false
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+torture.generator.divider false
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torture.generator.mul true
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torture.generator.divider true
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torture.generator.run_twice true
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torture.generator.mix.xmem 10
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@ -69,10 +67,10 @@ index a677d2d..ec0745f 100644
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def rand_seglen() = rand_range(0, 7)
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def rand_imm() = rand_range(-2048, 2047)
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diff --git a/generator/src/main/scala/SeqALU.scala b/generator/src/main/scala/SeqALU.scala
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index a1f27a5..e8957bf 100644
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index a1f27a5..18d6d7b 100644
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--- a/generator/src/main/scala/SeqALU.scala
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+++ b/generator/src/main/scala/SeqALU.scala
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@@ -68,15 +68,15 @@ class SeqALU(xregs: HWRegPool, use_mul: Boolean, use_div: Boolean) extends InstS
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@@ -68,17 +68,12 @@ class SeqALU(xregs: HWRegPool, use_mul: Boolean, use_div: Boolean) extends InstS
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candidates += seq_src1_immfn(SRAI, rand_shamt)
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candidates += seq_src1_immfn(ORI, rand_imm)
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candidates += seq_src1_immfn(ANDI, rand_imm)
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@ -80,19 +78,18 @@ index a1f27a5..e8957bf 100644
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- candidates += seq_src1_immfn(SLLIW, rand_shamtw)
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- candidates += seq_src1_immfn(SRLIW, rand_shamtw)
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- candidates += seq_src1_immfn(SRAIW, rand_shamtw)
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+ // candidates += seq_src1_immfn(ADDIW, rand_imm)
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+ // candidates += seq_src1_immfn(SLLIW, rand_shamtw)
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+ // candidates += seq_src1_immfn(SRLIW, rand_shamtw)
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+ // candidates += seq_src1_immfn(SRAIW, rand_shamtw)
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val oplist = new ArrayBuffer[Opcode]
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oplist += (ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND)
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- oplist += (ADDW, SUBW, SLLW, SRLW, SRAW)
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+ // oplist += (ADDW, SUBW, SLLW, SRLW, SRAW)
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if (use_mul) oplist += (MUL, MULH, MULHSU, MULHU, MULW)
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if (use_div) oplist += (DIV, DIVU, REM, REMU, DIVW, DIVUW, REMW, REMUW)
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- if (use_mul) oplist += (MUL, MULH, MULHSU, MULHU, MULW)
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- if (use_div) oplist += (DIV, DIVU, REM, REMU, DIVW, DIVUW, REMW, REMUW)
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+ if (use_mul) oplist += (MUL, MULH, MULHSU, MULHU)
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+ if (use_div) oplist += (DIV, DIVU, REM, REMU)
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for (op <- oplist)
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{
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diff --git a/generator/src/main/scala/SeqBranch.scala b/generator/src/main/scala/SeqBranch.scala
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index bba9895..0d257d7 100644
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--- a/generator/src/main/scala/SeqBranch.scala
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@ -116,7 +113,7 @@ index bba9895..0d257d7 100644
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insts += XOR(reg_mask, reg_mask, reg_one)
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insts += AND(reg_dst1, reg_src1, reg_mask)
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diff --git a/generator/src/main/scala/SeqMem.scala b/generator/src/main/scala/SeqMem.scala
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index 3c180ed..1feb1d3 100644
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index 3c180ed..89200f6 100644
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--- a/generator/src/main/scala/SeqMem.scala
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+++ b/generator/src/main/scala/SeqMem.scala
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@@ -51,7 +51,7 @@ class SeqMem(xregs: HWRegPool, mem: Mem, use_amo: Boolean) extends InstSeq
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@ -128,20 +125,17 @@ index 3c180ed..1feb1d3 100644
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if (is_store)
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{
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if (typ == byte || typ ==ubyte) (SB, dw_addr + rand_addr_b(8))
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@@ -110,13 +110,13 @@ class SeqMem(xregs: HWRegPool, mem: Mem, use_amo: Boolean) extends InstSeq
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@@ -110,13 +110,10 @@ class SeqMem(xregs: HWRegPool, mem: Mem, use_amo: Boolean) extends InstSeq
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candidates += seq_load_addrfn(LH, rand_addr_h)
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candidates += seq_load_addrfn(LHU, rand_addr_h)
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candidates += seq_load_addrfn(LW, rand_addr_w)
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- candidates += seq_load_addrfn(LWU, rand_addr_w)
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- candidates += seq_load_addrfn(LD, rand_addr_d)
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+ // candidates += seq_load_addrfn(LWU, rand_addr_w)
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+ // candidates += seq_load_addrfn(LD, rand_addr_d)
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candidates += seq_store_addrfn(SB, rand_addr_b)
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candidates += seq_store_addrfn(SH, rand_addr_h)
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candidates += seq_store_addrfn(SW, rand_addr_w)
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- candidates += seq_store_addrfn(SD, rand_addr_d)
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+ // candidates += seq_store_addrfn(SD, rand_addr_d)
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if (use_amo)
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{
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@ -15,7 +15,7 @@ fi
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## Compile test case and create reference
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riscv32-unknown-elf-gcc -m32 -march=RV32IC -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -o test.elf test.S
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riscv32-unknown-elf-gcc -m32 -march=RV32IMC -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -o test.elf test.S
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LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf > test.ref
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riscv32-unknown-elf-objcopy -O binary test.elf test.bin
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python3 ../../firmware/makehex.py test.bin 4096 > test.hex
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@ -38,7 +38,9 @@ module testbench (
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end
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picorv32 #(
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.COMPRESSED_ISA(1)
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.COMPRESSED_ISA(1),
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.ENABLE_MUL(1),
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.ENABLE_DIV(1)
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) uut (
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.clk (clk ),
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.resetn (resetn ),
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