mirror of https://github.com/YosysHQ/picorv32.git
Added resource utilization to xilinx eval
This commit is contained in:
parent
1f99de5117
commit
094dc690bb
39
README.md
39
README.md
|
@ -10,8 +10,8 @@ PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wi
|
|||
(a license that is similar in terms to the MIT license or the 2-clause BSD license).
|
||||
|
||||
|
||||
Features and Typical Applications:
|
||||
----------------------------------
|
||||
Features and Typical Applications
|
||||
---------------------------------
|
||||
|
||||
- Small (~1000 LUTs in a 7-Series Xilinx FGPA)
|
||||
- High fMAX (~250 MHz on 7-Series Xilinx FGPAs)
|
||||
|
@ -57,8 +57,8 @@ non-branching instructions in an external coprocessor. An implementation
|
|||
of a core that implements the `MUL[H[SU|U]]` instructions is provided.
|
||||
|
||||
|
||||
Files in this Repository:
|
||||
-------------------------
|
||||
Files in this Repository
|
||||
------------------------
|
||||
|
||||
#### README.md
|
||||
|
||||
|
@ -102,8 +102,8 @@ Another simple test firmware that runs the Dhrystome benchmark.
|
|||
Various scripts and examples for different (synthesis) tools and hardware architectures.
|
||||
|
||||
|
||||
Parameters:
|
||||
-----------
|
||||
Verilog Module Parameters
|
||||
-------------------------
|
||||
|
||||
The following Verilog module parameters can be used to configure the PicoRV32
|
||||
core.
|
||||
|
@ -168,8 +168,8 @@ The start address of the program.
|
|||
The start address of the interrupt handler.
|
||||
|
||||
|
||||
Performance:
|
||||
------------
|
||||
Cycles per Instruction Performance
|
||||
----------------------------------
|
||||
|
||||
*A short reminder: This core is optimized for size, not performance.*
|
||||
|
||||
|
@ -344,8 +344,8 @@ Example:
|
|||
timer x1, x2
|
||||
|
||||
|
||||
Building a pure RV32I Toolchain:
|
||||
--------------------------------
|
||||
Building a pure RV32I Toolchain
|
||||
-------------------------------
|
||||
|
||||
The default settings in the [riscv-tools](https://github.com/riscv/riscv-tools) build
|
||||
scripts will build a compiler, assembler and linker that can target any RISC-V ISA,
|
||||
|
@ -374,12 +374,12 @@ makes it easy to install them side-by-side with the regular riscv-tools, which
|
|||
are using the name prefix `riscv64-unknown-elf-` by default.
|
||||
|
||||
|
||||
Evaluation: Timing on Xilinx 7-Series FPGAs
|
||||
-------------------------------------------
|
||||
Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs
|
||||
-----------------------------------------------------------
|
||||
|
||||
The following table lists the maximum clock speeds that PicoRV32 can run at on
|
||||
Xilinx 7-Series FPGAs. This are the values reported by Vivado 2015.1 post
|
||||
place&route static timing analysis (report_timing).
|
||||
place&route static timing analysis with `report_timing`.
|
||||
|
||||
| Device | Speedgrade | Clock Period (Freq.) |
|
||||
|:-------------------- |:----------:| --------------------:|
|
||||
|
@ -393,6 +393,18 @@ place&route static timing analysis (report_timing).
|
|||
| Xilinx Virtex-7T | -2 | 2.6 ns (384 MHz) |
|
||||
| Xilinx Virtex-7T | -3 | 2.4 ns (416 MHz) |
|
||||
|
||||
The following table lists the resource utilization in area-optimized synthesis,
|
||||
as reported by Vivado 2015.1 post optimization with `report_utilization`. The
|
||||
"small" core is PicoRV32 configured down to a RV32E cpu, the "regular" core is
|
||||
PicoRV32 with its default settings and the "large" core is PicoRV32 with
|
||||
enabled PCPI, IRQ and MUL features.
|
||||
|
||||
| Core Variant | Slice LUTs | LUTs as Memory |
|
||||
|:------------------ | ----------:| --------------:|
|
||||
| PicoRV32 "small" | 855 | 48 |
|
||||
| PicoRV32 "regular" | 996 | 48 |
|
||||
| PicoRV32 "large" | 1814 | 88 |
|
||||
|
||||
|
||||
Todos:
|
||||
------
|
||||
|
@ -401,5 +413,4 @@ Todos:
|
|||
- Optional write-through cache
|
||||
- Optional support for compressed ISA
|
||||
- Improved documentation and examples
|
||||
- Code cleanups and refactoring of main FSM
|
||||
|
||||
|
|
|
@ -1,5 +1,4 @@
|
|||
synth_*.log
|
||||
synth_*.mmi
|
||||
synth_*.bit
|
||||
synth_*.v
|
||||
tab_*/
|
||||
|
|
|
@ -1,12 +1,14 @@
|
|||
|
||||
read_verilog ../../picorv32.v
|
||||
read_verilog synth_area_top.v
|
||||
read_xdc synth_area.xdc
|
||||
|
||||
synth_design -part xc7k70t-fbg676 -top picorv32_axi
|
||||
opt_design
|
||||
# synth_design -part xc7k70t-fbg676 -top top_small
|
||||
# synth_design -part xc7k70t-fbg676 -top top_regular
|
||||
# synth_design -part xc7k70t-fbg676 -top top_large
|
||||
opt_design -resynth_seq_area
|
||||
|
||||
report_utilization
|
||||
# report_timing
|
||||
|
||||
write_verilog -force synth_area.v
|
||||
|
||||
|
|
|
@ -0,0 +1,143 @@
|
|||
|
||||
module top_small (
|
||||
input clk, resetn,
|
||||
output trap,
|
||||
|
||||
output mem_valid,
|
||||
output mem_instr,
|
||||
input mem_ready,
|
||||
|
||||
output [31:0] mem_addr,
|
||||
output [31:0] mem_wdata,
|
||||
output [ 3:0] mem_wstrb,
|
||||
input [31:0] mem_rdata
|
||||
);
|
||||
picorv32 #(
|
||||
.ENABLE_COUNTERS(0),
|
||||
.ENABLE_REGS_16_31(0),
|
||||
.ENABLE_REGS_DUALPORT(1),
|
||||
.LATCHED_MEM_RDATA(1)
|
||||
) picorv32 (
|
||||
.clk (clk ),
|
||||
.resetn (resetn ),
|
||||
.trap (trap ),
|
||||
.mem_valid(mem_valid),
|
||||
.mem_instr(mem_instr),
|
||||
.mem_ready(mem_ready),
|
||||
.mem_addr (mem_addr ),
|
||||
.mem_wdata(mem_wdata),
|
||||
.mem_wstrb(mem_wstrb),
|
||||
.mem_rdata(mem_rdata)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module top_regular (
|
||||
input clk, resetn,
|
||||
output trap,
|
||||
|
||||
output mem_valid,
|
||||
output mem_instr,
|
||||
input mem_ready,
|
||||
|
||||
output [31:0] mem_addr,
|
||||
output [31:0] mem_wdata,
|
||||
output [ 3:0] mem_wstrb,
|
||||
input [31:0] mem_rdata,
|
||||
|
||||
// Look-Ahead Interface
|
||||
output mem_la_read,
|
||||
output mem_la_write,
|
||||
output [31:0] mem_la_addr,
|
||||
output [31:0] mem_la_wdata,
|
||||
output [ 3:0] mem_la_wstrb
|
||||
);
|
||||
picorv32 picorv32 (
|
||||
.clk (clk ),
|
||||
.resetn (resetn ),
|
||||
.trap (trap ),
|
||||
.mem_valid (mem_valid ),
|
||||
.mem_instr (mem_instr ),
|
||||
.mem_ready (mem_ready ),
|
||||
.mem_addr (mem_addr ),
|
||||
.mem_wdata (mem_wdata ),
|
||||
.mem_wstrb (mem_wstrb ),
|
||||
.mem_rdata (mem_rdata ),
|
||||
.mem_la_read (mem_la_read ),
|
||||
.mem_la_write(mem_la_write),
|
||||
.mem_la_addr (mem_la_addr ),
|
||||
.mem_la_wdata(mem_la_wdata),
|
||||
.mem_la_wstrb(mem_la_wstrb)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module top_large (
|
||||
input clk, resetn,
|
||||
output trap,
|
||||
|
||||
output mem_valid,
|
||||
output mem_instr,
|
||||
input mem_ready,
|
||||
|
||||
output [31:0] mem_addr,
|
||||
output [31:0] mem_wdata,
|
||||
output [ 3:0] mem_wstrb,
|
||||
input [31:0] mem_rdata,
|
||||
|
||||
// Look-Ahead Interface
|
||||
output mem_la_read,
|
||||
output mem_la_write,
|
||||
output [31:0] mem_la_addr,
|
||||
output [31:0] mem_la_wdata,
|
||||
output [ 3:0] mem_la_wstrb,
|
||||
|
||||
// Pico Co-Processor Interface (PCPI)
|
||||
output pcpi_insn_valid,
|
||||
output [31:0] pcpi_insn,
|
||||
output pcpi_rs1_valid,
|
||||
output [31:0] pcpi_rs1,
|
||||
output pcpi_rs2_valid,
|
||||
output [31:0] pcpi_rs2,
|
||||
input pcpi_rd_valid,
|
||||
input [31:0] pcpi_rd,
|
||||
input pcpi_wait,
|
||||
input pcpi_ready,
|
||||
|
||||
// IRQ Interface
|
||||
input [31:0] irq,
|
||||
output [31:0] eoi
|
||||
);
|
||||
picorv32 #(
|
||||
.ENABLE_PCPI(1),
|
||||
.ENABLE_MUL(1),
|
||||
.ENABLE_IRQ(1)
|
||||
) picorv32 (
|
||||
.clk (clk ),
|
||||
.resetn (resetn ),
|
||||
.trap (trap ),
|
||||
.mem_valid (mem_valid ),
|
||||
.mem_instr (mem_instr ),
|
||||
.mem_ready (mem_ready ),
|
||||
.mem_addr (mem_addr ),
|
||||
.mem_wdata (mem_wdata ),
|
||||
.mem_wstrb (mem_wstrb ),
|
||||
.mem_rdata (mem_rdata ),
|
||||
.mem_la_read (mem_la_read ),
|
||||
.mem_la_write (mem_la_write ),
|
||||
.mem_la_addr (mem_la_addr ),
|
||||
.mem_la_wdata (mem_la_wdata ),
|
||||
.mem_la_wstrb (mem_la_wstrb ),
|
||||
.pcpi_insn_valid(pcpi_insn_valid),
|
||||
.pcpi_insn (pcpi_insn ),
|
||||
.pcpi_rs1_valid (pcpi_rs1_valid ),
|
||||
.pcpi_rs1 (pcpi_rs1 ),
|
||||
.pcpi_rs2_valid (pcpi_rs2_valid ),
|
||||
.pcpi_rs2 (pcpi_rs2 ),
|
||||
.pcpi_rd_valid (pcpi_rd_valid ),
|
||||
.pcpi_rd (pcpi_rd ),
|
||||
.pcpi_wait (pcpi_wait ),
|
||||
.pcpi_ready (pcpi_ready ),
|
||||
.irq (irq ),
|
||||
.eoi (eoi )
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -11,5 +11,3 @@ route_design
|
|||
report_utilization
|
||||
report_timing
|
||||
|
||||
write_verilog -force synth_speed.v
|
||||
|
||||
|
|
Loading…
Reference in New Issue