mirror of https://github.com/YosysHQ/picorv32.git
Revert "Fix RISCV_FORMAL_BLACKBOX_REGS (broke liveness on branch ops)"
This reverts commit 624bc05f98
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picorv32.v
20
picorv32.v
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@ -1301,27 +1301,27 @@ module picorv32 #(
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end
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always @(posedge clk) begin
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if (resetn && cpuregs_write && latched_rd) begin
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`ifndef RISCV_FORMAL_BLACKBOX_REGS
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if (resetn && cpuregs_write && latched_rd)
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cpuregs[latched_rd] <= cpuregs_wrdata;
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`else
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// blackbox regs on write side because branching instructions
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// require a stable value on register read port, abstracting
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// on the read port in the block below would be more efficient
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// but would require a more complex abstraction.
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cpuregs[latched_rd] <= $anyseq;
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`endif
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end
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end
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always @* begin
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decoded_rs = 'bx;
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if (ENABLE_REGS_DUALPORT) begin
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`ifndef RISCV_FORMAL_BLACKBOX_REGS
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cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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`else
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cpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
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cpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
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`endif
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end else begin
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decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
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`ifndef RISCV_FORMAL_BLACKBOX_REGS
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cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
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`else
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cpuregs_rs1 = decoded_rs ? $anyseq : 0;
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`endif
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cpuregs_rs2 = cpuregs_rs1;
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end
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end
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