mirror of https://github.com/YosysHQ/picorv32.git
Renamed rvfi_opcode to rvfi_insn
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@ -107,7 +107,7 @@ module picorv32 #(
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output reg [4:0] rvfi_rs1,
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output reg [4:0] rvfi_rs1,
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output reg [4:0] rvfi_rs2,
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output reg [4:0] rvfi_rs2,
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output reg [4:0] rvfi_rd,
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output reg [4:0] rvfi_rd,
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output reg [31:0] rvfi_opcode,
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output reg [31:0] rvfi_insn,
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output reg [31:0] rvfi_pre_pc,
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output reg [31:0] rvfi_pre_pc,
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output reg [31:0] rvfi_pre_rs1,
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output reg [31:0] rvfi_pre_rs1,
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output reg [31:0] rvfi_pre_rs2,
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output reg [31:0] rvfi_pre_rs2,
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@ -1862,7 +1862,7 @@ module picorv32 #(
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`ifdef RISCV_FORMAL
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`ifdef RISCV_FORMAL
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always @(posedge clk) begin
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always @(posedge clk) begin
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rvfi_valid <= resetn && launch_next_insn && dbg_valid_insn;
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rvfi_valid <= resetn && launch_next_insn && dbg_valid_insn;
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rvfi_opcode <= dbg_insn_opcode;
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rvfi_insn <= dbg_insn_opcode;
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rvfi_rs1 <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
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rvfi_rs1 <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
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rvfi_rs2 <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
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rvfi_rs2 <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
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rvfi_pre_pc <= dbg_insn_addr;
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rvfi_pre_pc <= dbg_insn_addr;
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