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Back to Vivado 2015.1
my synthesis license has a 2015.05 version limit..
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@ -533,10 +533,10 @@ place&route static timing analysis with `report_timing`.
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| Xilinx Virtex-7T | -3 | 2.4 ns (416 MHz) |
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The following table lists the resource utilization in area-optimized synthesis,
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as reported by Vivado 2015.2 post optimization with `report_utilization`.
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as reported by Vivado 2015.1 post optimization with `report_utilization`.
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PicoRV32 "small" is the core without counter instructions, with externally
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latched `mem_rdata`, and without catching of misaligned memory access and
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latched `mem_rdata`, and without catching of misaligned memory accesses and
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illegal instructions.
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PicoRV32 "regular" is simply the core with its default settings.
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@ -1,5 +1,5 @@
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export VIVADO = /opt/Xilinx/Vivado/2015.2/bin/vivado
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export VIVADO = /opt/Xilinx/Vivado/2015.1/bin/vivado
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help:
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@echo "Usage: make {synth_speed|synth_area|synth_soc}"
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