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Added insn timing hack to dryhstone testbench

This commit is contained in:
Clifford Wolf 2015-06-06 21:27:07 +02:00
parent bc8ffd2ecb
commit 2107a328c4
1 changed files with 15 additions and 1 deletions
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16
dhrystone/testbench.v
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@ -43,12 +43,14 @@ module testbench;
assign mem_ready = 1; assign mem_ready = 1;
always @(posedge clk) begin always @(posedge clk) begin
mem_rdata <= memory[mem_la_addr >> 2]; mem_rdata <= mem_la_read ? memory[mem_la_addr >> 2] : 'bx;
if (mem_valid) begin if (mem_valid) begin
case (mem_addr) case (mem_addr)
32'h1000_0000: begin 32'h1000_0000: begin
`ifndef INSN_TIMING
$write("%c", mem_wdata); $write("%c", mem_wdata);
$fflush(); $fflush();
`endif
end end
default: begin default: begin
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0]; if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
@ -72,4 +74,16 @@ module testbench;
$finish; $finish;
end end
end end
`ifdef INSN_TIMING
initial begin
repeat (100000) @(posedge clk);
$finish;
end
always @(uut.count_instr[0]) begin
// iverilog -DINSN_TIMING testbench.v ../picorv32.v && ./a.out > x
// sed 's,.*## ,,' x | gawk 'x != "" {print x,$2-y;} {x=$1;y=$2;}' | sort | uniq -c | sort -k3 -n
$display("## %-s %d", uut.instruction, uut.count_cycle);
end
`endif
endmodule endmodule