mirror of https://github.com/YosysHQ/picorv32.git
Added scripts/csmith/ verilator support
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parent
96831d720f
commit
211fb521a8
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@ -1,3 +1,4 @@
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obj_dir
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riscv-fesvr
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riscv-isa-sim
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output_ref.txt
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@ -2,16 +2,36 @@ RISCV_TOOLS_DIR = /opt/riscv32imc
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RISCV_TOOLS_PREFIX = $(RISCV_TOOLS_DIR)/bin/riscv32-unknown-elf-
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CSMITH_INCDIR = $(shell ls -d /usr/local/include/csmith-* | head -n1)
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CC = $(RISCV_TOOLS_PREFIX)gcc
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SHELL = /bin/bash
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run: test_ref test.hex testbench.vvp
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help:
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@echo "Usage: make { loop | verilator | iverilog | spike }"
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loop:
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+set -e; x() { echo "$$*" >&2; "$$@"; }; while true; do \
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echo; echo; rm -f output_ref.txt output_sim.txt; \
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echo "-----------------------------------------"; \
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x rm -f test.hex test.elf test.c test_ref test.ld; \
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x $(MAKE) test_ref test.hex obj_dir/Vtestbench; \
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x timeout 1 ./test_ref > >( tee output_ref.txt; ) || { echo TIMEOUT; continue; }; \
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x obj_dir/Vtestbench > >( tee /dev/stderr | grep -v '$$finish' > output_sim.txt; ); \
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sleep 1; x diff -u output_ref.txt output_sim.txt; echo "OK."; \
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done
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verilator: test_ref test.hex obj_dir/Vtestbench
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./test_ref | tee output_ref.txt
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obj_dir/Vtestbench | grep -v '$$finish' | tee output_sim.txt
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diff -u output_ref.txt output_sim.txt
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iverilog: test_ref test.hex testbench.vvp
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./test_ref | tee output_ref.txt
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vvp -N testbench.vvp | tee output_sim.txt
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diff -u output_ref.txt output_sim.txt
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spike: riscv-fesvr/build.ok riscv-isa-sim/build.ok test_ref test.elf
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./test_ref | tee output_ref.txt
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LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf | tee output_spike.txt
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diff -u output_ref.txt output_spike.txt
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LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf | tee output_sim.txt
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diff -u output_ref.txt output_sim.txt
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riscv-fesvr/build.ok:
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rm -rf riscv-fesvr
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@ -31,6 +51,10 @@ testbench.vvp: testbench.v ../../picorv32.v
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iverilog -o testbench.vvp testbench.v ../../picorv32.v
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chmod -x testbench.vvp
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obj_dir/Vtestbench: testbench.v testbench.cc ../../picorv32.v
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verilator --exe -Wno-fatal --cc --top-module testbench testbench.v ../../picorv32.v testbench.cc
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$(MAKE) -C obj_dir -f Vtestbench.mk
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test.hex: test.elf
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$(RISCV_TOOLS_PREFIX)objcopy -O verilog test.elf test.hex
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@ -53,11 +77,11 @@ test.c:
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csmith --no-packed-struct -o test.c
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clean:
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rm -f platform.info test.c test.ld test.elf test.hex test_ref testbench.vvp testbench.vcd
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rm -f output_ref.txt output_sim.txt output_spike.txt
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rm -rf platform.info test.c test.ld test.elf test.hex test_ref obj_dir
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rm -rf testbench.vvp testbench.vcd output_ref.txt output_sim.txt
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mrproper: clean
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rm -rf riscv-fesvr riscv-isa-sim
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.PHONY: run spike clean mrproper
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.PHONY: help loop verilator iverilog spike clean mrproper
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@ -0,0 +1,18 @@
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#include "Vtestbench.h"
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#include "verilated.h"
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int main(int argc, char **argv, char **env)
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{
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Verilated::commandArgs(argc, argv);
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Vtestbench* top = new Vtestbench;
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top->clk = 0;
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while (!Verilated::gotFinish()) {
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top->clk = !top->clk;
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top->eval();
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}
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delete top;
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exit(0);
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}
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@ -1,19 +1,30 @@
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`timescale 1 ns / 1 ps
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module testbench;
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module testbench (
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`ifdef VERILATOR
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input clk
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`endif
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);
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`ifndef VERILATOR
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reg clk = 1;
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reg resetn = 0;
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wire trap;
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always #5 clk = ~clk;
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`endif
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reg resetn = 0;
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integer resetn_cnt = 0;
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wire trap;
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initial begin
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// $dumpfile("testbench.vcd");
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// $dumpvars(0, testbench);
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repeat (100) @(posedge clk);
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resetn <= 1;
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end
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always @(posedge clk) begin
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if (resetn_cnt < 100)
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resetn_cnt <= resetn_cnt + 1;
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else
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resetn <= 1;
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end
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wire mem_valid;
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wire mem_instr;
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@ -53,7 +64,9 @@ module testbench;
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always @(posedge clk) begin
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if (mem_valid && mem_wstrb && mem_addr == 'h10000000) begin
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$write("%c", mem_wdata[ 7: 0]);
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`ifndef VERILATOR
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$fflush;
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`endif
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end else begin
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if (mem_valid && mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
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if (mem_valid && mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
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@ -64,7 +77,7 @@ module testbench;
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always @(posedge clk) begin
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if (resetn && trap) begin
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repeat (10) @(posedge clk);
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// repeat (10) @(posedge clk);
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// $display("TRAP");
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$finish;
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end
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