mirror of https://github.com/YosysHQ/picorv32.git
- fix missed timer interrupts,
when another interrupt activates shortly before
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parent
e308982e18
commit
258d63d476
13
picorv32.v
13
picorv32.v
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@ -1435,15 +1435,9 @@ module picorv32 #(
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next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
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if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
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if (timer - 1 == 0)
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next_irq_pending[irq_timer] = 1;
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timer <= timer - 1;
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end
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if (ENABLE_IRQ) begin
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next_irq_pending = next_irq_pending | irq;
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end
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decoder_trigger <= mem_do_rinst && mem_done;
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decoder_trigger_q <= decoder_trigger;
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decoder_pseudo_trigger <= 0;
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@ -1913,6 +1907,13 @@ module picorv32 #(
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end
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endcase
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if (ENABLE_IRQ) begin
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next_irq_pending = next_irq_pending | irq;
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if ENABLE_IRQ_TIMER && timer
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if (timer - 1 == 0)
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next_irq_pending[irq_timer] = 1;
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end
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if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
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if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
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`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
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