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picorv32
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- fix missed timer interrupts, 

when another interrupt activates shortly before
This commit is contained in:
Robert Korn 2020-03-27 07:26:48 +01:00
parent e308982e18
commit 258d63d476
1 changed files with 7 additions and 6 deletions
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13
picorv32.v
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@ -1435,15 +1435,9 @@ module picorv32 #(
next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx; next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
if (timer - 1 == 0)
next_irq_pending[irq_timer] = 1;
timer <= timer - 1; timer <= timer - 1;
end end
if (ENABLE_IRQ) begin
next_irq_pending = next_irq_pending | irq;
end
decoder_trigger <= mem_do_rinst && mem_done; decoder_trigger <= mem_do_rinst && mem_done;
decoder_trigger_q <= decoder_trigger; decoder_trigger_q <= decoder_trigger;
decoder_pseudo_trigger <= 0; decoder_pseudo_trigger <= 0;
@ -1913,6 +1907,13 @@ module picorv32 #(
end end
endcase endcase
if (ENABLE_IRQ) begin
next_irq_pending = next_irq_pending | irq;
if ENABLE_IRQ_TIMER && timer
if (timer - 1 == 0)
next_irq_pending[irq_timer] = 1;
end
if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);) `debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)