mirror of https://github.com/YosysHQ/picorv32.git
Streamlined debug signals
This commit is contained in:
Clifford Wolf
parent
49aef71641
commit
262a9085bb
149
picorv32.v
149
picorv32.v
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@ -20,6 +20,7 @@
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`timescale 1 ns / 1 ps
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// `default_nettype none
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// `define DEBUGREGS
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// `define DEBUGASM
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// `define DEBUG
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`ifdef DEBUG
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@ -110,8 +111,9 @@ module picorv32 #(
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reg [31:0] cpuregs [0:regfile_size-1];
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reg [4:0] reg_sh;
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reg [31:0] current_insn;
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reg [31:0] current_insn_addr;
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reg [31:0] next_insn_opcode;
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reg [31:0] dbg_insn_opcode;
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reg [31:0] dbg_insn_addr;
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assign pcpi_rs1 = reg_op1;
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assign pcpi_rs2 = reg_op2;
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@ -124,38 +126,38 @@ module picorv32 #(
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reg [31:0] timer;
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`ifdef DEBUGREGS
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wire [31:0] reg_x0 = cpuregs[0];
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wire [31:0] reg_x1 = cpuregs[1];
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wire [31:0] reg_x2 = cpuregs[2];
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wire [31:0] reg_x3 = cpuregs[3];
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wire [31:0] reg_x4 = cpuregs[4];
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wire [31:0] reg_x5 = cpuregs[5];
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wire [31:0] reg_x6 = cpuregs[6];
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wire [31:0] reg_x7 = cpuregs[7];
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wire [31:0] reg_x8 = cpuregs[8];
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wire [31:0] reg_x9 = cpuregs[9];
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wire [31:0] reg_x10 = cpuregs[10];
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wire [31:0] reg_x11 = cpuregs[11];
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wire [31:0] reg_x12 = cpuregs[12];
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wire [31:0] reg_x13 = cpuregs[13];
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wire [31:0] reg_x14 = cpuregs[14];
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wire [31:0] reg_x15 = cpuregs[15];
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wire [31:0] reg_x16 = cpuregs[16];
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wire [31:0] reg_x17 = cpuregs[17];
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wire [31:0] reg_x18 = cpuregs[18];
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wire [31:0] reg_x19 = cpuregs[19];
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wire [31:0] reg_x20 = cpuregs[20];
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wire [31:0] reg_x21 = cpuregs[21];
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wire [31:0] reg_x22 = cpuregs[22];
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wire [31:0] reg_x23 = cpuregs[23];
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wire [31:0] reg_x24 = cpuregs[24];
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wire [31:0] reg_x25 = cpuregs[25];
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wire [31:0] reg_x26 = cpuregs[26];
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wire [31:0] reg_x27 = cpuregs[27];
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wire [31:0] reg_x28 = cpuregs[28];
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wire [31:0] reg_x29 = cpuregs[29];
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wire [31:0] reg_x30 = cpuregs[30];
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wire [31:0] reg_x31 = cpuregs[31];
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wire [31:0] dbg_reg_x0 = cpuregs[0];
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wire [31:0] dbg_reg_x1 = cpuregs[1];
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wire [31:0] dbg_reg_x2 = cpuregs[2];
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wire [31:0] dbg_reg_x3 = cpuregs[3];
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wire [31:0] dbg_reg_x4 = cpuregs[4];
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wire [31:0] dbg_reg_x5 = cpuregs[5];
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wire [31:0] dbg_reg_x6 = cpuregs[6];
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wire [31:0] dbg_reg_x7 = cpuregs[7];
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wire [31:0] dbg_reg_x8 = cpuregs[8];
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wire [31:0] dbg_reg_x9 = cpuregs[9];
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wire [31:0] dbg_reg_x10 = cpuregs[10];
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wire [31:0] dbg_reg_x11 = cpuregs[11];
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wire [31:0] dbg_reg_x12 = cpuregs[12];
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wire [31:0] dbg_reg_x13 = cpuregs[13];
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wire [31:0] dbg_reg_x14 = cpuregs[14];
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wire [31:0] dbg_reg_x15 = cpuregs[15];
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wire [31:0] dbg_reg_x16 = cpuregs[16];
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wire [31:0] dbg_reg_x17 = cpuregs[17];
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wire [31:0] dbg_reg_x18 = cpuregs[18];
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wire [31:0] dbg_reg_x19 = cpuregs[19];
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wire [31:0] dbg_reg_x20 = cpuregs[20];
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wire [31:0] dbg_reg_x21 = cpuregs[21];
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wire [31:0] dbg_reg_x22 = cpuregs[22];
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wire [31:0] dbg_reg_x23 = cpuregs[23];
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wire [31:0] dbg_reg_x24 = cpuregs[24];
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wire [31:0] dbg_reg_x25 = cpuregs[25];
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wire [31:0] dbg_reg_x26 = cpuregs[26];
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wire [31:0] dbg_reg_x27 = cpuregs[27];
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wire [31:0] dbg_reg_x28 = cpuregs[28];
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wire [31:0] dbg_reg_x29 = cpuregs[29];
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wire [31:0] dbg_reg_x30 = cpuregs[30];
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wire [31:0] dbg_reg_x31 = cpuregs[31];
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`endif
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// Internal PCPI Cores
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@ -307,6 +309,7 @@ module picorv32 #(
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always @(posedge clk) begin
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if (mem_xfer) begin
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mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
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next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
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end
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if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
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@ -432,9 +435,6 @@ module picorv32 #(
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prefetched_high_word <= 0;
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end else case (mem_state)
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0: begin
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if (mem_do_prefetch || mem_do_rinst) begin
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current_insn_addr <= next_pc;
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end
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if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
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mem_valid <= !mem_la_use_prefetched_high_word;
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mem_instr <= mem_do_prefetch || mem_do_rinst;
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@ -533,9 +533,13 @@ module picorv32 #(
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assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
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reg [63:0] new_ascii_instr;
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`FORMAL_KEEP reg [63:0] ascii_instr;
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`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
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`FORMAL_KEEP reg [31:0] dbg_insn_imm;
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`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
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`FORMAL_KEEP reg [4:0] dbg_insn_rs2;
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`FORMAL_KEEP reg [4:0] dbg_insn_rd;
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always @(posedge clk) begin
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always @* begin
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new_ascii_instr = "";
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if (instr_lui) new_ascii_instr = "lui";
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@ -591,18 +595,47 @@ module picorv32 #(
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if (instr_maskirq) new_ascii_instr = "maskirq";
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if (instr_waitirq) new_ascii_instr = "waitirq";
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if (instr_timer) new_ascii_instr = "timer";
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end
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if (decoder_trigger_q && !decoder_pseudo_trigger_q) begin
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ascii_instr <= new_ascii_instr;
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`ifdef DEBUG
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if (¤t_insn[1:0])
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$display("DECODE: 0x%08x 0x%08x %-0s", current_insn_addr, current_insn, new_ascii_instr ? new_ascii_instr : "UNKNOWN");
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else
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$display("DECODE: 0x%08x 0x%04x %-0s", current_insn_addr, current_insn[15:0], new_ascii_instr ? new_ascii_instr : "UNKNOWN");
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`endif
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always @(posedge clk) begin
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if (decoder_trigger && !decoder_pseudo_trigger) begin
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dbg_insn_addr <= next_pc;
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end
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end
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always @* begin
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if (decoder_trigger_q && !decoder_pseudo_trigger_q) begin
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dbg_ascii_instr = new_ascii_instr;
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if (&mem_rdata_q[1:0])
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dbg_insn_opcode = next_insn_opcode;
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else
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dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
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dbg_insn_imm = decoded_imm;
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dbg_insn_rs1 = decoded_rs1;
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dbg_insn_rs2 = decoded_rs2;
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dbg_insn_rd = decoded_rd;
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end
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end
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`ifdef DEBUGASM
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always @(posedge clk) begin
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if (decoder_trigger_q && !decoder_pseudo_trigger_q) begin
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$display("debugasm %x %x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
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end
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end
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`endif
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`ifdef DEBUG
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always @(posedge clk) begin
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if (decoder_trigger_q && !decoder_pseudo_trigger_q) begin
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if (&dbg_insn_opcode[1:0])
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$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
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else
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$display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
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end
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end
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`endif
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always @(posedge clk) begin
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is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
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is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
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@ -612,8 +645,6 @@ module picorv32 #(
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is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
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if (mem_do_rinst && mem_done) begin
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current_insn <= mem_rdata_latched;
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instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
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instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
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instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
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@ -886,18 +917,18 @@ module picorv32 #(
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reg [7:0] cpu_state;
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reg [1:0] irq_state;
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`FORMAL_KEEP reg [127:0] ascii_state;
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`FORMAL_KEEP reg [127:0] dbg_ascii_state;
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always @* begin
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ascii_state = "";
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if (cpu_state == cpu_state_trap) ascii_state = "trap";
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if (cpu_state == cpu_state_fetch) ascii_state = "fetch";
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if (cpu_state == cpu_state_ld_rs1) ascii_state = "ld_rs1";
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if (cpu_state == cpu_state_ld_rs2) ascii_state = "ld_rs2";
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if (cpu_state == cpu_state_exec) ascii_state = "exec";
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if (cpu_state == cpu_state_shift) ascii_state = "shift";
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if (cpu_state == cpu_state_stmem) ascii_state = "stmem";
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if (cpu_state == cpu_state_ldmem) ascii_state = "ldmem";
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dbg_ascii_state = "";
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if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap";
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if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch";
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if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
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if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
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if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec";
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if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift";
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if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem";
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if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
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end
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reg set_mem_do_rinst;
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