mirror of https://github.com/YosysHQ/picorv32.git
Added (by default disabled) register file access wires for debugging
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picorv32.v
34
picorv32.v
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@ -122,6 +122,40 @@ module picorv32 #(
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reg [31:0] irq_pending;
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reg [31:0] timer;
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generate if (0) begin:cpuregs_debug
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wire [31:0] reg_h00_x0 = cpuregs[0];
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wire [31:0] reg_h01_x1 = cpuregs[1];
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wire [31:0] reg_h02_x2 = cpuregs[2];
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wire [31:0] reg_h03_x3 = cpuregs[3];
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wire [31:0] reg_h04_x4 = cpuregs[4];
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wire [31:0] reg_h05_x5 = cpuregs[5];
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wire [31:0] reg_h06_x6 = cpuregs[6];
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wire [31:0] reg_h07_x7 = cpuregs[7];
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wire [31:0] reg_h08_x8 = cpuregs[8];
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wire [31:0] reg_h09_x9 = cpuregs[9];
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wire [31:0] reg_h0a_x10 = cpuregs[10];
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wire [31:0] reg_h0b_x11 = cpuregs[11];
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wire [31:0] reg_h0c_x12 = cpuregs[12];
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wire [31:0] reg_h0d_x13 = cpuregs[13];
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wire [31:0] reg_h0e_x14 = cpuregs[14];
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wire [31:0] reg_h0f_x15 = cpuregs[15];
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wire [31:0] reg_h10_x16 = cpuregs[16];
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wire [31:0] reg_h11_x17 = cpuregs[17];
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wire [31:0] reg_h12_x18 = cpuregs[18];
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wire [31:0] reg_h13_x19 = cpuregs[19];
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wire [31:0] reg_h14_x20 = cpuregs[20];
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wire [31:0] reg_h15_x21 = cpuregs[21];
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wire [31:0] reg_h16_x22 = cpuregs[22];
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wire [31:0] reg_h17_x23 = cpuregs[23];
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wire [31:0] reg_h18_x24 = cpuregs[24];
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wire [31:0] reg_h19_x25 = cpuregs[25];
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wire [31:0] reg_h1a_x26 = cpuregs[26];
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wire [31:0] reg_h1b_x27 = cpuregs[27];
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wire [31:0] reg_h1c_x28 = cpuregs[28];
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wire [31:0] reg_h1d_x29 = cpuregs[29];
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wire [31:0] reg_h1e_x30 = cpuregs[30];
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wire [31:0] reg_h1f_x31 = cpuregs[31];
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end endgenerate
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// Internal PCPI Cores
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