mirror of https://github.com/YosysHQ/picorv32.git
Added BARREL_SHIFTER config parameter
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Clifford Wolf
parent
0e9bdd0082
commit
2fdafb9c16
24
README.md
24
README.md
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@ -3,7 +3,7 @@ PicoRV32 - A Size-Optimized RISC-V CPU
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======================================
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PicoRV32 is a CPU core that implements the [RISC-V RV32IMC Instruction Set](http://riscv.org/).
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It can be configured to be a RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally
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It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally
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contains a built-in interrupt controller.
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Tools (gcc, binutils, etc..) can be obtained via the [RISC-V Website](http://riscv.org/download.html#tab_tools).
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@ -29,7 +29,7 @@ PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wi
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Features and Typical Applications
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---------------------------------
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- Small (750-1700 LUTs in 7-Series Xilinx Architecture)
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- Small (750-2000 LUTs in 7-Series Xilinx Architecture)
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- High f<sub>max</sub> (250-450 MHz on 7-Series Xilinx FPGAs)
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- Selectable native memory interface or AXI4-Lite master
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- Optional IRQ support (using a simple custom ISA)
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@ -170,6 +170,12 @@ of 4 bits and then shift in units of 1 bit. This speeds up shift operations,
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but adds additional hardware. Set this parameter to 0 to disable the two-stage
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shift to further reduce the size of the core.
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#### BARREL_SHIFTER (default = 0)
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By default shift operations are performed by successively shifting by a
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small amount (see `TWO_STAGE_SHIFT` above). With this option set, a barrel
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shifter is used instead instead.
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#### TWO_CYCLE_COMPARE (default = 0)
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This relaxes the longest data path a bit by adding an additional FF stage
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@ -294,9 +300,15 @@ in 40 cycles and a `MULH[SU|U]` instruction will execute in 72 cycles.
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When `ENABLE_DIV` is activated, then a `DIV[U]/REM[U]` instruction will
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execute in 40 cycles.
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Dhrystone benchmark results: 0.391 DMIPS/MHz (688 Dhrystones/Second/MHz)
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When `BARREL_SHIFTER` is activated, a shift operation takes as long as
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any other ALU operation.
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For the Dhrystone benchmark the average CPI is 4.110.
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The following dhrystone benchmark results are for a core with enabled
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`ENABLE_MUL`, `ENABLE_DIV`, and `BARREL_SHIFTER` options.
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Dhrystone benchmark results: 0.399 DMIPS/MHz (702 Dhrystones/Second/MHz)
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For the Dhrystone benchmark the average CPI is 4.030.
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PicoRV32 Native Memory Interface
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@ -586,7 +598,7 @@ once in advance.
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Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs
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-----------------------------------------------------------
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The following evaluations have been performed with Vivado 2015.1.
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The following evaluations have been performed with Vivado 2015.4.
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#### Timing on Xilinx 7-Series FPGAs
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@ -622,7 +634,7 @@ for the following three cores:
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- **PicoRV32 (regular):** The `picorv32` module in its default configuration.
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- **PicoRV32 (large):** The `picorv32` module with enabled PCPI, IRQ, MUL,
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DIV, and COMPRESSED_ISA features.
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DIV, BARREL_SHIFTER, and COMPRESSED_ISA features.
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See `make area` in [scripts/vivado/](scripts/vivado/).
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@ -27,6 +27,7 @@ module testbench;
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wire [3:0] mem_la_wstrb;
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picorv32 #(
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.BARREL_SHIFTER(1),
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.ENABLE_MUL(1),
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.ENABLE_DIV(1)
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) uut (
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26
picorv32.v
26
picorv32.v
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@ -43,6 +43,7 @@ module picorv32 #(
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] LATCHED_MEM_RDATA = 0,
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parameter [ 0:0] TWO_STAGE_SHIFT = 1,
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parameter [ 0:0] BARREL_SHIFTER = 0,
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parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
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parameter [ 0:0] TWO_CYCLE_ALU = 0,
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parameter [ 0:0] COMPRESSED_ISA = 0,
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@ -889,6 +890,7 @@ module picorv32 #(
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reg alu_wait, alu_wait_2;
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reg [31:0] alu_add_sub;
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reg [31:0] alu_shl, alu_shr;
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reg alu_eq, alu_ltu, alu_lts;
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generate if (TWO_CYCLE_ALU) begin
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@ -897,6 +899,8 @@ module picorv32 #(
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alu_eq <= reg_op1 == reg_op2;
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alu_lts <= $signed(reg_op1) < $signed(reg_op2);
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alu_ltu <= reg_op1 < reg_op2;
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alu_shl <= reg_op1 << reg_op2[4:0];
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alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
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end
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end else begin
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always @* begin
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@ -904,6 +908,8 @@ module picorv32 #(
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alu_eq = reg_op1 == reg_op2;
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alu_lts = $signed(reg_op1) < $signed(reg_op2);
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alu_ltu = reg_op1 < reg_op2;
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alu_shl = reg_op1 << reg_op2[4:0];
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alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
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end
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end endgenerate
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@ -938,6 +944,10 @@ module picorv32 #(
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alu_out = reg_op1 | reg_op2;
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instr_andi || instr_and:
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alu_out = reg_op1 & reg_op2;
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BARREL_SHIFTER && (instr_sll || instr_slli):
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alu_out = alu_shl;
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BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
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alu_out = alu_shr;
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endcase
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end
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@ -1208,16 +1218,16 @@ module picorv32 #(
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cpu_state <= cpu_state_ldmem;
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mem_do_rinst <= 1;
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end
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is_slli_srli_srai: begin
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is_slli_srli_srai && !BARREL_SHIFTER: begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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reg_sh <= decoded_rs2;
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cpu_state <= cpu_state_shift;
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end
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is_jalr_addi_slti_sltiu_xori_ori_andi: begin
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is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, decoded_rs1 ? cpuregs[decoded_rs1] : 0);)
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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reg_op2 <= decoded_imm;
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reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
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if (TWO_CYCLE_ALU)
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alu_wait <= 1;
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else
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@ -1237,7 +1247,7 @@ module picorv32 #(
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cpu_state <= cpu_state_stmem;
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mem_do_rinst <= 1;
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end
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is_sll_srl_sra: begin
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is_sll_srl_sra && !BARREL_SHIFTER: begin
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cpu_state <= cpu_state_shift;
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end
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default: begin
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@ -1284,7 +1294,7 @@ module picorv32 #(
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cpu_state <= cpu_state_stmem;
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mem_do_rinst <= 1;
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end
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is_sll_srl_sra: begin
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is_sll_srl_sra && !BARREL_SHIFTER: begin
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cpu_state <= cpu_state_shift;
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end
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default: begin
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@ -1299,8 +1309,6 @@ module picorv32 #(
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end
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cpu_state_exec: begin
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latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
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latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
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reg_out <= reg_pc + decoded_imm;
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if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
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mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
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@ -1308,6 +1316,8 @@ module picorv32 #(
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end else
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if (is_beq_bne_blt_bge_bltu_bgeu) begin
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latched_rd <= 0;
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latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
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latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
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if (mem_done)
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cpu_state <= cpu_state_fetch;
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if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
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@ -1704,6 +1714,7 @@ module picorv32_axi #(
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parameter [ 0:0] ENABLE_REGS_16_31 = 1,
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] TWO_STAGE_SHIFT = 1,
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parameter [ 0:0] BARREL_SHIFTER = 0,
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parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
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parameter [ 0:0] TWO_CYCLE_ALU = 0,
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parameter [ 0:0] COMPRESSED_ISA = 0,
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@ -1803,6 +1814,7 @@ module picorv32_axi #(
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.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
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.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
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.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
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.BARREL_SHIFTER (BARREL_SHIFTER ),
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.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
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.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
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.COMPRESSED_ISA (COMPRESSED_ISA ),
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@ -105,6 +105,7 @@ module top_large (
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);
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picorv32 #(
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.COMPRESSED_ISA(1),
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.BARREL_SHIFTER(1),
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.ENABLE_PCPI(1),
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.ENABLE_MUL(1),
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.ENABLE_IRQ(1)
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