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Update evaluation results to Vivado 2017.3
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README.md
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README.md
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@ -685,7 +685,7 @@ for an example of how to do that.
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Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs
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-----------------------------------------------------------
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The following evaluations have been performed with Vivado 2017.2.
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The following evaluations have been performed with Vivado 2017.3.
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#### Timing on Xilinx 7-Series FPGAs
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@ -699,14 +699,14 @@ See `make table.txt` in [scripts/vivado/](scripts/vivado/).
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| Device | Device | Speedgrade | Clock Period (Freq.) |
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|:------------------------- |:---------------------|:----------:| --------------------:|
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| Xilinx Kintex-7T | xc7k70t-fbg676-2 | -2 | 2.4 ns (416 MHz) |
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| Xilinx Kintex-7T | xc7k70t-fbg676-3 | -3 | 2.3 ns (434 MHz) |
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| Xilinx Kintex-7T | xc7k70t-fbg676-3 | -3 | 2.2 ns (454 MHz) |
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| Xilinx Virtex-7T | xc7v585t-ffg1761-2 | -2 | 2.3 ns (434 MHz) |
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| Xilinx Virtex-7T | xc7v585t-ffg1761-3 | -3 | 2.3 ns (434 MHz) |
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| Xilinx Kintex UltraScale | xcku035-fbva676-2-e | -2 | 2.1 ns (476 MHz) |
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| Xilinx Virtex-7T | xc7v585t-ffg1761-3 | -3 | 2.2 ns (454 MHz) |
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| Xilinx Kintex UltraScale | xcku035-fbva676-2-e | -2 | 2.0 ns (500 MHz) |
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| Xilinx Kintex UltraScale | xcku035-fbva676-3-e | -3 | 1.8 ns (555 MHz) |
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| Xilinx Virtex UltraScale | xcvu065-ffvc1517-2-e | -2 | 1.9 ns (526 MHz) |
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| Xilinx Virtex UltraScale | xcvu065-ffvc1517-3-e | -3 | 1.8 ns (555 MHz) |
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| Xilinx Kintex UltraScale+ | xcku3p-ffva676-2-e | -2 | 1.5 ns (666 MHz) |
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| Xilinx Virtex UltraScale | xcvu065-ffvc1517-2-e | -2 | 2.1 ns (476 MHz) |
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| Xilinx Virtex UltraScale | xcvu065-ffvc1517-3-e | -3 | 2.0 ns (500 MHz) |
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| Xilinx Kintex UltraScale+ | xcku3p-ffva676-2-e | -2 | 1.4 ns (714 MHz) |
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| Xilinx Kintex UltraScale+ | xcku3p-ffva676-3-e | -3 | 1.3 ns (769 MHz) |
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| Xilinx Virtex UltraScale+ | xcvu3p-ffvc1517-2-e | -2 | 1.5 ns (666 MHz) |
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| Xilinx Virtex UltraScale+ | xcvu3p-ffvc1517-3-e | -3 | 1.4 ns (714 MHz) |
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@ -729,7 +729,7 @@ See `make area` in [scripts/vivado/](scripts/vivado/).
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| Core Variant | Slice LUTs | LUTs as Memory | Slice Registers |
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|:------------------ | ----------:| --------------:| ---------------:|
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| PicoRV32 (small) | 757 | 48 | 442 |
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| PicoRV32 (regular) | 910 | 48 | 583 |
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| PicoRV32 (large) | 2090 | 88 | 1085 |
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| PicoRV32 (small) | 761 | 48 | 442 |
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| PicoRV32 (regular) | 917 | 48 | 583 |
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| PicoRV32 (large) | 2019 | 88 | 1085 |
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@ -1,5 +1,5 @@
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VIVADO_BASE = /opt/Xilinx/Vivado/2017.2
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VIVADO_BASE = /opt/Xilinx/Vivado/2017.3
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VIVADO = $(VIVADO_BASE)/bin/vivado
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XVLOG = $(VIVADO_BASE)/bin/xvlog
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XELAB = $(VIVADO_BASE)/bin/xelab
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