mirror of https://github.com/YosysHQ/picorv32.git
Fixed "make timing" in dhrystone/
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@ -91,8 +91,9 @@ module testbench;
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repeat (100000) @(posedge clk);
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$finish;
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end
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always @(uut.count_instr[0]) begin
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$display("## %-s %d", uut.ascii_instr ? uut.ascii_instr : "x", uut.count_cycle);
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always @(posedge clk) begin
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if (uut.decoder_trigger_q && !uut.decoder_pseudo_trigger_q)
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$display("## %-s %d", uut.dbg_ascii_instr ? uut.dbg_ascii_instr : "x", uut.count_cycle);
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end
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`endif
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endmodule
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