Single test support in scripts/torture/

scripts/torture/Makefile

@@ -1,6 +1,6 @@
 
-run_signle_test: riscv-torture/build.ok riscv-isa-sim/build.ok
+test: riscv-torture/build.ok riscv-isa-sim/build.ok
-	bash run_single_test.sh
+	bash test.sh
 
 riscv-torture/build.ok: riscv-torture-rv32.diff
 	rm -rf riscv-torture
@@ -22,7 +22,7 @@ riscv-isa-sim/build.ok: riscv-fesvr/build.ok
 
 clean:
 	rm -rf riscv-torture riscv-fesvr riscv-isa-sim
-	rm -f test.S test.elf test.ref
+	rm -f test.S test.elf test.bin test.hex test.ref test.vvp
 
-.PHONY: run_signle_test clean
+.PHONY: test clean
 

scripts/torture/run_single_test.sh

@@ -1,18 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-
-## Generate test case
-
-cd riscv-torture
-./sbt generator/run
-cp output/test.S ../test.S
-cd ..
-
-
-## Compile test case and create reference
-
-riscv32-unknown-elf-gcc -m32 -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -o test.elf test.S
-LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf > test.ref
-

scripts/torture/test.sh

@@ -0,0 +1,28 @@
+#!/bin/bash
+
+set -ex
+
+
+## Generate test case
+
+if ! test -f test.S; then
+	cd riscv-torture
+	./sbt generator/run
+	cp output/test.S ../test.S
+	cd ..
+fi
+
+
+## Compile test case and create reference
+
+riscv32-unknown-elf-gcc -m32 -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -o test.elf test.S
+LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf > test.ref
+riscv32-unknown-elf-objcopy -O binary test.elf test.bin
+python3 ../../firmware/makehex.py test.bin 4096 > test.hex
+
+
+## Run test
+
+iverilog -o test.vvp testbench.v ../../picorv32.v
+vvp test.vvp +hex=test.hex +ref=test.ref
+

scripts/torture/testbench.v

@@ -0,0 +1,83 @@
+module testbench (
+`ifdef VERILATOR
+	input clk
+`endif
+);
+`ifndef VERILATOR
+	reg clk = 1;
+	always #5 clk = ~clk;
+`endif
+	reg resetn = 0;
+	wire trap;
+
+	wire        mem_valid;
+	wire        mem_instr;
+	reg         mem_ready;
+	wire [31:0] mem_addr;
+	wire [31:0] mem_wdata;
+	wire [3:0]  mem_wstrb;
+	reg  [31:0] mem_rdata;
+
+	picorv32 #(
+	) uut (
+		.clk         (clk         ),
+		.resetn      (resetn      ),
+		.trap        (trap        ),
+		.mem_valid   (mem_valid   ),
+		.mem_instr   (mem_instr   ),
+		.mem_ready   (mem_ready   ),
+		.mem_addr    (mem_addr    ),
+		.mem_wdata   (mem_wdata   ),
+		.mem_wstrb   (mem_wstrb   ),
+		.mem_rdata   (mem_rdata   )
+	);
+
+	reg [1023:0] hex_filename;
+	reg [1023:0] ref_filename;
+
+	reg [31:0] memory [0:4095];
+	reg [31:0] memory_ref [0:4095];
+	integer i, errcount;
+
+	initial begin
+		if ($value$plusargs("hex=%s", hex_filename)) $readmemh(hex_filename, memory);
+		if ($value$plusargs("ref=%s", ref_filename)) $readmemh(ref_filename, memory_ref);
+		// $dumpfile("testbench.vcd");
+		// $dumpvars(0, testbench);
+
+		repeat (10) @(posedge clk);
+		resetn <= 1;
+	end
+
+	always @(posedge clk) begin
+		mem_ready <= 0;
+		mem_rdata <= 'bx;
+
+		if (!trap || !resetn) begin
+			if (mem_valid && !mem_ready && resetn) begin
+				mem_ready <= 1;
+				if (mem_wstrb) begin
+					if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
+					if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
+					if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
+					if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
+				end else begin
+					mem_rdata <= memory[mem_addr >> 2];
+				end
+			end
+		end else begin
+			errcount = 0;
+			for (i=0; i < 4096; i=i+1) begin
+				if (memory[i] !== memory_ref[i]) begin
+					$display("Signature check failed at %04x: mem=%08x ref=%08x", i << 2, memory[i], memory_ref[i]);
+					errcount = errcount + 1;
+				end
+			end
+			if (errcount)
+				$display("FAILED: Got %1d errors for %1s/%1s!", errcount, hex_filename, ref_filename);
+			else
+				$display("PASSED %1s/%1s.", hex_filename, ref_filename);
+			$finish;
+		end
+	end
+endmodule