mirror of https://github.com/YosysHQ/picorv32.git
Added support for dual-port register file
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Clifford Wolf
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60867e10a9
commit
34d9dea8c7
69
README.md
69
README.md
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@ -43,30 +43,65 @@ memory-mapped peripherals, communicating with each other using the native
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interface, and communicating with the outside world via AXI4.
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Parameters:
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-----------
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The following Verilog module parameters can be used to configure the PicoRV32
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core.
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### ENABLE_COUNTERS (default = 1)
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This parameter enables support for the `RDCYCLE[H]`, `RDTIME[H]`, and
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`RDINSTRET[H]` instructions. This instructions will cause a hardware
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trap (like any other unsupported instruction) if `ENABLE_COUNTERS` is set to zero.
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*Note: Strictly speaking the `RDCYCLE[H]`, `RDTIME[H]`, and `RDINSTRET[H]`
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instructions are not optional for an RV32I core. But chances are they are not
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going to be missed after the application code has been debugged and profiled.
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This instructions are optional for an RV32E core.*
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### ENABLE_REGS_16_31 (default = 1)
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This parameter enables support for registers the `x16`..`x31`. The RV32E ISA
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excludes this registers. However, the RV32E ISA spec requires a hardware trap
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for when code tries to access this registers. This is not implemented in PicoRV32.
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### ENABLE_REGS_DUALPORT (default = 1)
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The register file can be implemented with two or one read ports. A dual ported
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register file improves performance a bit, but can also increase the size of
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the core.
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Performance:
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------------
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The average Cycles per Instruction (CPI) is 4 to 6, depending on the mix of
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instructions in the code. The CPI numbers for the individual instructions are:
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*A short reminder: This core is optimized for size, not performance.*
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| Instruction | CPI |
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| ---------------------| ----:|
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| direct jump (jal) | 3 |
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| ALU reg + immediate | 3 |
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| ALU reg + reg | 4 |
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| branch (not taken) | 4 |
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| memory load | 5 |
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| memory store | 6 |
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| branch (taken) | 6 |
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| indirect jump (jalr) | 6 |
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| shift operations | 4-15 |
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Unless stated otherwise, the following numbers apply to a PicoRV32 with
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ENABLE_REGS_DUALPORT active and connected to a memory that can accomodate
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requests within one clock cycle.
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Dhrystone benchmark results: 0.280 DMIPS/MHz (493 Dhrystones/Second/MHz)
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The average Cycles per Instruction (CPI) is 4 to 5, depending on the mix of
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instructions in the code. The CPI numbers for the individual instructions
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can be found in the following table. (The column "CPI (SP)" contains the
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CPI numbers for a core built without ENABLE_REGS_DUALPORT.)
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For the Dryhstone benchmark the average CPI is 4.606.
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| Instruction | CPI | CPI (SP) |
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| ---------------------| ----:| --------:|
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| direct jump (jal) | 3 | 3 |
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| ALU reg + immediate | 3 | 3 |
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| ALU reg + reg | 3 | 4 |
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| branch (not taken) | 3 | 4 |
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| memory load | 5 | 5 |
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| memory store | 5 | 6 |
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| branch (taken) | 5 | 6 |
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| indirect jump (jalr) | 6 | 6 |
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| shift operations | 4-14 | 4-15 |
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*This numbers apply to systems with memory that can accomodate requests within
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one clock cycle. Slower memory will degrade the performance of the processor.*
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Dhrystone benchmark results: 0.309 DMIPS/MHz (544 Dhrystones/Second/MHz)
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For the Dryhstone benchmark the average CPI is 4.167.
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Todos:
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26
picorv32.v
26
picorv32.v
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@ -27,7 +27,8 @@
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module picorv32 #(
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parameter ENABLE_COUNTERS = 1,
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parameter ENABLE_REGS_16_31 = 1
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parameter ENABLE_REGS_16_31 = 1,
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parameter ENABLE_REGS_DUALPORT = 1
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) (
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input clk, resetn,
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output reg trap,
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@ -529,6 +530,21 @@ module picorv32 #(
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reg_op2 <= decoded_imm;
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mem_do_rinst <= mem_do_prefetch;
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cpu_state <= cpu_state_exec;
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end else if (ENABLE_REGS_DUALPORT) begin
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`ifdef DEBUG
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$display("LD_RS2: %2d 0x%08x", decoded_rs2, decoded_rs2 ? cpuregs[decoded_rs2] : 0);
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`endif
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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if (is_sb_sh_sw) begin
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cpu_state <= cpu_state_stmem;
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mem_do_rinst <= 1;
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end else if (is_sll_srl_sra) begin
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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cpu_state <= cpu_state_shift;
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end else begin
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mem_do_rinst <= mem_do_prefetch;
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cpu_state <= cpu_state_exec;
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end
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end else
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cpu_state <= cpu_state_ld_rs2;
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end
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@ -689,7 +705,8 @@ endmodule
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module picorv32_axi #(
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parameter ENABLE_COUNTERS = 1,
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parameter ENABLE_REGS_16_31 = 1
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parameter ENABLE_REGS_16_31 = 1,
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parameter ENABLE_REGS_DUALPORT = 1
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) (
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input clk, resetn,
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output trap,
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@ -756,8 +773,9 @@ module picorv32_axi #(
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);
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picorv32 #(
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.ENABLE_COUNTERS (ENABLE_COUNTERS ),
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.ENABLE_REGS_16_31(ENABLE_REGS_16_31)
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.ENABLE_COUNTERS (ENABLE_COUNTERS ),
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.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
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.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT)
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) picorv32_core (
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.clk (clk ),
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.resetn (resetn ),
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