mirror of https://github.com/YosysHQ/picorv32.git
Merge branch 'master' into icebreaker-spram
This commit is contained in:
Clifford Wolf
GitHub
commit
358dde2376
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@ -29,6 +29,7 @@
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/testbench.gtkw
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/testbench.vcd
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/testbench.trace
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/testbench_verilator*
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/check.smt2
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/check.vcd
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/synth.log
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@ -653,6 +653,14 @@ void cmd_benchmark_all()
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}
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#endif
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void cmd_echo()
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{
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print("Return to menu by sending '!'\n\n");
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char c;
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while ((c = getchar()) != '!')
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putchar(c);
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}
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// --------------------------------------------------------
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void main()
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@ -703,6 +711,7 @@ void main()
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print(" [0] Benchmark all configs\n");
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print(" [M] Run Memtest\n");
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print(" [S] Print SPI state\n");
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print(" [e] Echo UART\n");
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print("\n");
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for (int rep = 10; rep > 0; rep--)
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@ -748,6 +757,9 @@ void main()
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case 'P':
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cmd_print_spi_state();
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break;
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case 'e':
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cmd_echo();
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break;
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default:
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continue;
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}
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@ -1,74 +1,104 @@
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TOOLCHAIN_PREFIX = riscv32-unknown-elf-
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ICE40_SIM_CELLS=$(shell yosys-config --datdir/ice40/cells_sim.v)
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# set to 4 for simulation
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FIRMWARE_COUNTER_BITS=18
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all: example.bin
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## -------------------
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## firmware generation
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firmware.elf: firmware.S firmware.c firmware.lds
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$(TOOLCHAIN_PREFIX)gcc -Os -ffreestanding -nostdlib -o firmware.elf firmware.S firmware.c \
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--std=gnu99 -Wl,-Bstatic,-T,firmware.lds,-Map,firmware.map,--strip-debug -lgcc
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chmod -x firmware.elf
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$(TOOLCHAIN_PREFIX)gcc \
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-DSHIFT_COUNTER_BITS=$(FIRMWARE_COUNTER_BITS) \
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-march=rv32i -Os -ffreestanding -nostdlib \
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-o $@ firmware.S firmware.c \
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--std=gnu99 -Wl,-Bstatic,-T,firmware.lds,-Map,firmware.map,--strip-debug
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chmod -x $@
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firmware.bin: firmware.elf
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$(TOOLCHAIN_PREFIX)objcopy -O binary firmware.elf firmware.bin
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chmod -x firmware.bin
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$(TOOLCHAIN_PREFIX)objcopy -O binary $< $@
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chmod -x $@
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firmware.hex: firmware.bin
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python3 ../../firmware/makehex.py firmware.bin 128 > firmware.hex
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python3 ../../firmware/makehex.py $< 128 > $@
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synth.blif: example.v ../../picorv32.v firmware.hex
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yosys -v3 -l synth.log -p 'synth_ice40 -top top -blif $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
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## ------------------------------
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## main flow: synth/p&r/bitstream
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example.asc: synth.blif
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arachne-pnr -d 8k -o example.asc -p example.pcf synth.blif
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synth.json: example.v ../../picorv32.v firmware.hex
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yosys -v3 -l synth.log -p 'synth_ice40 -top top -json $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
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example.asc: synth.json example.pcf
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nextpnr-ice40 --hx8k --package ct256 --json $< --pcf example.pcf --asc $@
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example.bin: example.asc
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icepack example.asc example.bin
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icepack $< $@
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example_tb.vvp: example_tb.v example.v firmware.hex
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iverilog -o example_tb.vvp -s testbench example.v example_tb.v ../../picorv32.v
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chmod -x example_tb.vvp
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## -----------------
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## icarus simulation
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example_tb.vvp: example.v example_tb.v ../../picorv32.v firmware.hex
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iverilog -o $@ -s testbench $(filter %.v, $^)
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chmod -x $@
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example_sim: example_tb.vvp
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vvp -N example_tb.vvp
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vvp -N $<
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example_sim_vcd: example_tb.vvp
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vvp -N example_tb.vvp +vcd
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vvp -N $< +vcd
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synth_tb.vvp: example_tb.v synth.blif
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iverilog -o synth_tb.vvp -s testbench synth.v example_tb.v `yosys-config --datdir/ice40/cells_sim.v`
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chmod -x synth_tb.vvp
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## ---------------------
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## post-synth simulation
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synth_tb.vvp: example_tb.v synth.json
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iverilog -o $@ -s testbench synth.v example_tb.v $(ICE40_SIM_CELLS)
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chmod -x $@
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synth_sim: synth_tb.vvp
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vvp -N synth_tb.vvp
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vvp -N $<
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synth_sim_vcd: synth_tb.vvp
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vvp -N synth_tb.vvp +vcd
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vvp -N $< +vcd
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route.v: example.asc
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icebox_vlog -L -n top -sp example.pcf example.asc > route.v
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## ---------------------
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## post-route simulation
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route_tb.vvp: example_tb.v route.v
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iverilog -o route_tb.vvp -s testbench route.v example_tb.v `yosys-config --datdir/ice40/cells_sim.v`
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chmod -x route_tb.vvp
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route.v: example.asc example.pcf
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icebox_vlog -L -n top -sp example.pcf $< > $@
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route_tb.vvp: route.v example_tb.v
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iverilog -o $@ -s testbench $^ $(ICE40_SIM_CELLS)
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chmod -x $@
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route_sim: route_tb.vvp
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vvp -N route_tb.vvp
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vvp -N $<
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route_sim_vcd: route_tb.vvp
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vvp -N route_tb.vvp +vcd
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vvp -N $< +vcd
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prog_sram:
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iceprog -S example.bin
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## ---------------------
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## miscellaneous targets
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view:
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gtkwave example.vcd example.gtkw
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prog_sram: example.bin
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iceprog -S $<
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timing: example.asc example.pcf
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icetime -c 62 -tmd hx8k -P ct256 -p example.pcf -t $<
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view: example.vcd
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gtkwave $< example.gtkw
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## ------
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## el fin
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clean:
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rm -f firmware.elf firmware.map firmware.bin firmware.hex
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rm -f synth.log synth.v synth.blif route.v example.asc example.bin
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rm -f synth.log synth.v synth.json route.v example.asc example.bin
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rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd
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.PHONY: all prog_sram view clean
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.PHONY: example_sim synth_sim route_sim
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.PHONY: example_sim synth_sim route_sim timing
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.PHONY: example_sim_vcd synth_sim_vcd route_sim_vcd
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@ -1,7 +1,8 @@
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#include <stdint.h>
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// use SHIFT_COUNTER_BITS=4 for simulation
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#define SHIFT_COUNTER_BITS 18
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#ifndef SHIFT_COUNTER_BITS
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#error SHIFT_COUNTER_BITS must be defined as 4 (for simulation) or 18 (for hardware bitstreams)!
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#endif
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void output(uint8_t c)
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{
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@ -0,0 +1,12 @@
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To build the example LED-blinking firmware for an HX8K Breakout Board and get
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a timing report (checked against the default 12MHz oscillator):
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$ make clean example.bin timing
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To run all the simulation tests:
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$ make clean example_sim synth_sim route_sim FIRMWARE_COUNTER_BITS=4
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(You must run the `clean` target to rebuild the firmware with the updated
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`FIRMWARE_COUNTER_BITS` parameter; the firmware source must be recompiled for
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simulation vs hardware, but this is not tracked as a Makefile dependency.)
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@ -0,0 +1,6 @@
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Use UCB-BAR's RISC-V Torture Test Generator to test PicoRV32.
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You might need to install the following addition dependecies:
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sudo apt-get install python3-pip
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pip3 install numpy
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@ -0,0 +1,139 @@
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# nix.shell: PicoRV32 Development Environment
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#
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# This file allows you to use the Nix Package Manager (https://nixos.org/nix)
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# in order to download, install, and prepare a working environment for doing
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# PicoRV32/PicoSoC development on _any_ existing Linux distribution, provided
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# the Nix package manager is installed.
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#
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# Current included tools:
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#
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# - Synthesis: Recent Yosys and SymbiYosys
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# - Place and Route: arachne-pnr and nextpnr (ICE40, ECP5, Python, no GUI)
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# - Packing: Project IceStorm (Trellis tools may be included later?)
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# - SMT Solvers: Z3 4.7.x, Yices 2.6.x, and Boolector 3.0.x
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# - Verification: Recent Verilator, Recent (unreleased) Icarus Verilog
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# - A bare-metal RISC-V cross compiler toolchain, based on GCC 8.2.x
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#
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# With these tools, you can immediately begin development, simulation, firmware
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# hacking, etc with almost no need to fiddle with recent tools yourself. Almost
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# all of the tools will be downloaded on-demand (except the GCC toolchain)
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# meaning you don't have to compile any recent tools yourself. Due to the
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# "hermetic" nature of Nix, these packages should also work on practically any
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# Linux distribution, as well.
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#
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# (This environment should also be suitable for running riscv-formal test
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# harnesses on PicoRV32, as well. In fact it is probably useful for almost
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# _any_ RTL implementation of the RV32I core.)
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#
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# Usage
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# -----
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#
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# At the top-level of the picorv32 directory, simply run the 'nix-shell' command,
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# which will then drop you into a bash prompt:
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#
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#
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# $ nix-shell
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# ...
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# [nix-shell:~/src/picorv32]$
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#
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#
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# When you run 'nix-shell', you will automatically begin downloading all of the
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# various tools you need from an upstream "cache", so most of this will execute
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# very quickly. However, this may take a while, as you will at least have to
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# build a cross-compiled RISC-V toolchain, which may take some time. (These
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# binaries are not available from the cache, so they must be built by you.) Once
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# you have done this once, you do not need to do it again.
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#
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# At this point, once you are inside the shell, you can begin running tests
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# like normal. For example, to run the Verilator tests with the included test
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# firmware, which is substantially faster than Icarus:
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#
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# [nix-shell:~/src/picorv32]$ make test_verilator TOOLCHAIN_PREFIX=riscv32-unknown-elf-
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# ...
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#
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#
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# Note that you must override TOOLCHAIN_PREFIX (in the top-level Makefile, it
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# looks in /opt by default).
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#
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# This will work immediately with no extra fiddling necessary. You can also run
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# formal verification tests using a provided SMT solver, for example, yices and
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# boolector (Z3 is not used since it does not complete in a reasonable amount
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||||
# of time for these examples):
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#
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# [nix-shell:~/src/picorv32]$ make check-yices check-boolector
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# ...
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#
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# You can also run the PicoSoC tests and build bitstreams. To run the
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# simulation tests and then build bitstreams for the HX8K and IceBreaker
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# boards:
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#
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||||
# [nix-shell:~/src/picorv32]$ cd picosoc/
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# [nix-shell:~/src/picorv32/picosoc]$ make hx8ksynsim icebsynsim
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# ...
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# [nix-shell:~/src/picorv32/picosoc]$ make hx8kdemo.bin icebreaker.bin
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# ...
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#
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# The HX8K simulation and IceBreaker simulation will be synthesized with Yosys
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# and then run with Icarus Verilog. The bitstreams for HX8K and IceBreaker will
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# be P&R'd with arachne-pnr and nextpnr, respectively.
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#
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{ architecture ? "rv32imc"
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||||
}:
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||||
# TODO FIXME: fix this to a specific version of nixpkgs.
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||||
# ALSO: maybe use cachix to make it easier for contributors(?)
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||||
with import <nixpkgs> {};
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||||
let
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||||
# risc-v toolchain source code. TODO FIXME: this should be replaced with
|
||||
# upstream versions of GCC. in the future we could also include LLVM (the
|
||||
# upstream nixpkgs LLVM expression should be built with it in time)
|
||||
riscv-toolchain-ver = "8.2.0";
|
||||
riscv-src = pkgs.fetchFromGitHub {
|
||||
owner = "riscv";
|
||||
repo = "riscv-gnu-toolchain";
|
||||
rev = "c3ad5556197e374c25bc475ffc9285b831f869f8";
|
||||
sha256 = "1j9y3ai42xzzph9rm116sxfzhdlrjrk4z0v4yrk197j72isqyxbc";
|
||||
fetchSubmodules = true;
|
||||
};
|
||||
|
||||
# given an architecture like 'rv32i', this will generate the given
|
||||
# toolchain derivation based on the above source code.
|
||||
make-riscv-toolchain = arch:
|
||||
stdenv.mkDerivation rec {
|
||||
name = "riscv-${arch}-toolchain-${version}";
|
||||
version = "${riscv-toolchain-ver}-${builtins.substring 0 7 src.rev}";
|
||||
src = riscv-src;
|
||||
|
||||
configureFlags = [ "--with-arch=${arch}" ];
|
||||
installPhase = ":"; # 'make' installs on its own
|
||||
hardeningDisable = [ "all" ];
|
||||
enableParallelBuilding = true;
|
||||
|
||||
# Stripping/fixups break the resulting libgcc.a archives, somehow.
|
||||
# Maybe something in stdenv that does this...
|
||||
dontStrip = true;
|
||||
dontFixup = true;
|
||||
|
||||
nativeBuildInputs = with pkgs; [ curl gawk texinfo bison flex gperf ];
|
||||
buildInputs = with pkgs; [ libmpc mpfr gmp expat ];
|
||||
};
|
||||
|
||||
riscv-toolchain = make-riscv-toolchain architecture;
|
||||
|
||||
# These are all the packages that will be available inside the nix-shell
|
||||
# environment.
|
||||
buildInputs = with pkgs;
|
||||
# these are generally useful packages for tests, verification, synthesis
|
||||
# and deployment, etc
|
||||
[ python3 gcc
|
||||
yosys symbiyosys nextpnr arachne-pnr icestorm
|
||||
z3 boolector yices
|
||||
verilog verilator
|
||||
# also include the RISC-V toolchain
|
||||
riscv-toolchain
|
||||
];
|
||||
|
||||
# Export a usable shell environment
|
||||
in runCommand "picorv32-shell" { inherit buildInputs; } ""
|
||||
Loading…
Reference in New Issue