Make synth_area_small work

This commit is contained in:
Tom Verbeure 2016-08-30 22:24:48 -07:00
parent 29e90e4dff
commit 36152a5688
5 changed files with 16 additions and 20 deletions

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@ -1,12 +1,10 @@
QUARTUS_ROOTDIR = /opt/altera_lite/16.0
QUARTUS_BIN = $(QUARTUS_ROOTDIR)/quartus/bin
export QUARTUS_ROOTDIR = /opt/altera_lite/16.0
export QUARTUS_BIN = $(QUARTUS_ROOTDIR)/quartus/bin
VLOG = iverilog
TOOLCHAIN_PREFIX = /opt/riscv32i/bin/riscv32-unknown-elf-
export VIVADO
help:
@echo ""
@echo "Simple synthesis tests:"
@ -24,10 +22,13 @@ help:
synth_%:
rm -f $@.log
$(VIVADO) -nojournal -log $@.log -mode batch -source $@.tcl
rm -rf .Xil fsm_encoding.os synth_*.backup.log usage_statistics_webtalk.*
-grep -B4 -A10 'Slice LUTs' $@.log
-grep -B1 -A9 ^Slack $@.log && echo
mkdir -p $@_build
cp $@.qsf $@_build
cd $@_build && $(QUARTUS_BIN)/quartus_map $@.qsf
cd $@_build && $(QUARTUS_BIN)/quartus_fit --read_settings_files=off -write_settings_files=off $@ -c $@
cd $@_build && $(QUARTUS_BIN)/quartus_sta $@ -c $@
-cd $@_build && grep -A3 "Total logic elements" output_files/$@.fit.summary
-cd $@_build && grep -B1 "Slack" output_files/$@.sta.summary
synth_system: firmware.hex
@ -56,5 +57,5 @@ table.txt:
clean:
rm -rf firmware.bin firmware.elf firmware.hex firmware.map synth_*.log
rm -rf synth_*.mmi synth_*.bit synth_system.v table.txt tab_*/ webtalk.jou
rm -rf synth_*.mmi synth_*.bit synth_system.v table.txt tab_*/

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@ -0,0 +1,6 @@
set_global_assignment -name DEVICE ep4ce30f23c7
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name TOP_LEVEL_ENTITY top_small
set_global_assignment -name VERILOG_FILE ../synth_area_top.v
set_global_assignment -name VERILOG_FILE ../../../picorv32.v
set_global_assignment -name SDC_FILE ../synth_area.sdc

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@ -1,10 +0,0 @@
read_verilog ../../picorv32.v
read_verilog synth_area_top.v
read_xdc synth_area.xdc
synth_design -part xc7k70t-fbg676 -top top_small
opt_design -sweep -propconst -resynth_seq_area
opt_design -directive ExploreSequentialArea
report_utilization
report_timing

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@ -1 +0,0 @@
create_clock -period 2.50 [get_ports clk]