mirror of https://github.com/YosysHQ/picorv32.git
Make synth_area_small work
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parent
29e90e4dff
commit
36152a5688
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@ -1,12 +1,10 @@
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QUARTUS_ROOTDIR = /opt/altera_lite/16.0
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QUARTUS_BIN = $(QUARTUS_ROOTDIR)/quartus/bin
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export QUARTUS_ROOTDIR = /opt/altera_lite/16.0
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export QUARTUS_BIN = $(QUARTUS_ROOTDIR)/quartus/bin
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VLOG = iverilog
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TOOLCHAIN_PREFIX = /opt/riscv32i/bin/riscv32-unknown-elf-
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export VIVADO
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help:
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@echo ""
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@echo "Simple synthesis tests:"
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@ -24,10 +22,13 @@ help:
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synth_%:
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rm -f $@.log
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$(VIVADO) -nojournal -log $@.log -mode batch -source $@.tcl
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rm -rf .Xil fsm_encoding.os synth_*.backup.log usage_statistics_webtalk.*
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-grep -B4 -A10 'Slice LUTs' $@.log
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-grep -B1 -A9 ^Slack $@.log && echo
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mkdir -p $@_build
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cp $@.qsf $@_build
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cd $@_build && $(QUARTUS_BIN)/quartus_map $@.qsf
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cd $@_build && $(QUARTUS_BIN)/quartus_fit --read_settings_files=off -write_settings_files=off $@ -c $@
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cd $@_build && $(QUARTUS_BIN)/quartus_sta $@ -c $@
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-cd $@_build && grep -A3 "Total logic elements" output_files/$@.fit.summary
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-cd $@_build && grep -B1 "Slack" output_files/$@.sta.summary
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synth_system: firmware.hex
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@ -56,5 +57,5 @@ table.txt:
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clean:
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rm -rf firmware.bin firmware.elf firmware.hex firmware.map synth_*.log
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rm -rf synth_*.mmi synth_*.bit synth_system.v table.txt tab_*/ webtalk.jou
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rm -rf synth_*.mmi synth_*.bit synth_system.v table.txt tab_*/
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@ -0,0 +1,6 @@
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set_global_assignment -name DEVICE ep4ce30f23c7
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name TOP_LEVEL_ENTITY top_small
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set_global_assignment -name VERILOG_FILE ../synth_area_top.v
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set_global_assignment -name VERILOG_FILE ../../../picorv32.v
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set_global_assignment -name SDC_FILE ../synth_area.sdc
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@ -1,10 +0,0 @@
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read_verilog ../../picorv32.v
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read_verilog synth_area_top.v
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read_xdc synth_area.xdc
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synth_design -part xc7k70t-fbg676 -top top_small
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opt_design -sweep -propconst -resynth_seq_area
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opt_design -directive ExploreSequentialArea
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report_utilization
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report_timing
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@ -1 +0,0 @@
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create_clock -period 2.50 [get_ports clk]
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