mirror of https://github.com/YosysHQ/picorv32.git
Merge pull request #131 from tomverbeure/dhry_trace
Add tracing support to dhrystone test
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commit
3bb692a954
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@ -13,6 +13,10 @@ endif
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test: testbench.vvp dhry.hex
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vvp -N testbench.vvp
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test_trace: testbench.vvp dhry.hex
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vvp -N $< +trace
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python3 ../showtrace.py testbench.trace dhry.elf > testbench.ins
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test_nola: testbench_nola.vvp dhry.hex
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vvp -N testbench_nola.vvp
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@ -26,12 +26,16 @@ module testbench;
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wire [31:0] mem_la_wdata;
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wire [3:0] mem_la_wstrb;
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wire trace_valid;
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wire [35:0] trace_data;
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picorv32 #(
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.BARREL_SHIFTER(1),
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.ENABLE_FAST_MUL(1),
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.ENABLE_DIV(1),
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.PROGADDR_RESET('h10000),
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.STACKADDR('h10000)
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.STACKADDR('h10000),
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.ENABLE_TRACE(1)
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) uut (
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.clk (clk ),
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.resetn (resetn ),
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@ -47,7 +51,9 @@ module testbench;
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.mem_la_write(mem_la_write),
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.mem_la_addr (mem_la_addr ),
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.mem_la_wdata(mem_la_wdata),
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.mem_la_wstrb(mem_la_wstrb)
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.mem_la_wstrb(mem_la_wstrb),
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.trace_valid (trace_valid),
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.trace_data (trace_data )
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);
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reg [7:0] memory [0:256*1024-1];
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@ -83,6 +89,22 @@ module testbench;
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$dumpvars(0, testbench);
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end
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integer trace_file;
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initial begin
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if ($test$plusargs("trace")) begin
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trace_file = $fopen("testbench.trace", "w");
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repeat (10) @(posedge clk);
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while (!trap) begin
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@(posedge clk);
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if (trace_valid)
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$fwrite(trace_file, "%x\n", trace_data);
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end
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$fclose(trace_file);
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$display("Finished writing testbench.trace.");
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end
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end
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always @(posedge clk) begin
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if (resetn && trap) begin
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repeat (10) @(posedge clk);
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