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Improve testbench_verilator 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-05-25 13:04:49 +02:00
parent 247a19dd58
commit 3f55fb4ccb
2 changed files with 30 additions and 19 deletions
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8
Makefile
View File

@ -71,8 +71,9 @@ testbench_synth.vvp: testbench.v synth.v
chmod -x $@
testbench_verilator: testbench.v picorv32.v
verilator -Wno-lint -Wno-MULTIDRIVEN -trace --top-module picorv32_wrapper --cc testbench.v picorv32.v --exe testbench.cc $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA))
$(MAKE) -C obj_dir -f Vpicorv32_wrapper.mk
verilator --cc --exe -Wno-lint -trace --top-module picorv32_wrapper testbench.v picorv32.v testbench.cc \
$(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) --Mdir testbench_verilator_dir
$(MAKE) -C testbench_verilator_dir -f Vpicorv32_wrapper.mk
cp obj_dir/Vpicorv32_wrapper testbench_verilator
check: check-yices
@ -170,6 +171,7 @@ clean:
rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) check.smt2 check.vcd synth.v synth.log \
firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
testbench.vvp testbench_sp.vvp testbench_synth.vvp testbench_ez.vvp \
testbench_rvf.vvp testbench_wb.vvp testbench.vcd testbench.trace
testbench_rvf.vvp testbench_wb.vvp testbench.vcd testbench.trace \
testbench_verilator testbench_verilator_dir
.PHONY: test test_vcd test_sp test_axi test_wb test_wb_vcd test_ez test_ez_vcd test_synth download-tools build-tools toc clean

41
testbench.v
View File

@ -275,30 +275,32 @@ module axi4_memory #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
) (
/* verilator lint_off MULTIDRIVEN */
input clk,
input mem_axi_awvalid,
output reg mem_axi_awready = 0,
input [31:0] mem_axi_awaddr,
input [ 2:0] mem_axi_awprot,
output reg mem_axi_awready,
input [31:0] mem_axi_awaddr,
input [ 2:0] mem_axi_awprot,
input mem_axi_wvalid,
output reg mem_axi_wready = 0,
input [31:0] mem_axi_wdata,
input [ 3:0] mem_axi_wstrb,
input mem_axi_wvalid,
output reg mem_axi_wready,
input [31:0] mem_axi_wdata,
input [ 3:0] mem_axi_wstrb,
output reg mem_axi_bvalid = 0,
input mem_axi_bready,
output reg mem_axi_bvalid,
input mem_axi_bready,
input mem_axi_arvalid,
output reg mem_axi_arready = 0,
input [31:0] mem_axi_araddr,
input [ 2:0] mem_axi_arprot,
input mem_axi_arvalid,
output reg mem_axi_arready,
input [31:0] mem_axi_araddr,
input [ 2:0] mem_axi_arprot,
output reg mem_axi_rvalid = 0,
output reg mem_axi_rvalid,
input mem_axi_rready,
output reg [31:0] mem_axi_rdata,
output reg tests_passed
output reg tests_passed
);
reg [31:0] memory [0:64*1024/4-1] /* verilator public */;
reg verbose;
@ -307,7 +309,14 @@ module axi4_memory #(
reg axi_test;
initial axi_test = $test$plusargs("axi_test") || AXI_TEST;
initial tests_passed = 0;
initial begin
mem_axi_awready = 0;
mem_axi_wready = 0;
mem_axi_bvalid = 0;
mem_axi_arready = 0;
mem_axi_rvalid = 0;
tests_passed = 0;
end
reg [63:0] xorshift64_state = 64'd88172645463325252;