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Fix initialization of "irq" in verilog testbench

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-09-22 13:59:43 +02:00
parent 881f928e05
commit 3f9b5048bc
2 changed files with 2 additions and 2 deletions
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2
testbench.v
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@ -75,7 +75,7 @@ module picorv32_wrapper #(
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq;
reg [31:0] irq = 0;
reg [15:0] count_cycle = 0;
always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0;

2
testbench_wb.v
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@ -65,7 +65,7 @@ module picorv32_wrapper #(
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq;
reg [31:0] irq = 0;
wire mem_instr;
reg [15:0] count_cycle = 0;