mirror of https://github.com/YosysHQ/picorv32.git
Moved ENABLE_MUL from picorv32_axi to picorv32
This commit is contained in:
Clifford Wolf
parent
818faffe25
commit
4c15e05298
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@ -102,10 +102,9 @@ Set this to 1 to enable the Pico Co-Processor Interface (PCPI).
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#### ENABLE_MUL (default = 0)
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This parameter is only available on the `picorv32_axi` core. It internally
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enables PCPI and instantiates the `picorv32_pcpi_mul` core that implements
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the `MUL[H[SU|U]]` instructions. The external CPCI interface only becomes
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functional when ENABLE_PCPI is set as well.
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This parameter internally enables PCPI and instantiates the `picorv32_pcpi_mul`
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core that implements the `MUL[H[SU|U]]` instructions. The external CPCI
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interface only becomes functional when ENABLE_PCPI is set as well.
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#### ENABLE_IRQ (default = 0)
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137
picorv32.v
137
picorv32.v
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@ -31,6 +31,7 @@ module picorv32 #(
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parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
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parameter [ 0:0] LATCHED_MEM_RDATA = 0,
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parameter [ 0:0] ENABLE_PCPI = 0,
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parameter [ 0:0] ENABLE_MUL = 0,
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parameter [ 0:0] ENABLE_IRQ = 0,
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parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
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parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
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@ -79,6 +80,8 @@ module picorv32 #(
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localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ;
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localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ;
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localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL;
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reg [63:0] count_cycle, count_instr;
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reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out, reg_alu_out;
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reg [31:0] cpuregs [0:regfile_size-1];
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@ -94,6 +97,61 @@ module picorv32 #(
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reg [31:0] irq_pending;
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reg [31:0] timer;
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// Internal PCPI Cores
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wire pcpi_mul_rd_valid;
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wire [31:0] pcpi_mul_rd;
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wire pcpi_mul_wait;
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wire pcpi_mul_ready;
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reg pcpi_int_rd_valid;
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reg [31:0] pcpi_int_rd;
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reg pcpi_int_wait;
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reg pcpi_int_ready;
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generate if (ENABLE_MUL) begin
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picorv32_pcpi_mul pcpi_mul (
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.clk (clk ),
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.resetn (resetn ),
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.pcpi_insn_valid(pcpi_insn_valid ),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1_valid (pcpi_rs1_valid ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2_valid (pcpi_rs2_valid ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_rd_valid (pcpi_mul_rd_valid),
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.pcpi_rd (pcpi_mul_rd ),
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.pcpi_wait (pcpi_mul_wait ),
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.pcpi_ready (pcpi_mul_ready )
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);
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end else begin
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assign pcpi_mul_rd_valid = 0;
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assign pcpi_mul_rd = 1'bx;
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assign pcpi_mul_wait = 0;
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assign pcpi_mul_ready = 0;
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end endgenerate
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always @* begin
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pcpi_int_rd_valid = 0;
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pcpi_int_rd = 1'bx;
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pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, ENABLE_MUL && pcpi_mul_wait};
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pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, ENABLE_MUL && pcpi_mul_ready};
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(* parallel_case *)
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case (1'b1)
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ENABLE_PCPI && pcpi_ready: begin
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pcpi_int_rd_valid = pcpi_rd_valid;
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pcpi_int_rd = pcpi_rd;
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end
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ENABLE_MUL && pcpi_mul_ready: begin
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pcpi_int_rd_valid = pcpi_mul_rd_valid;
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pcpi_int_rd = pcpi_mul_rd;
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end
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endcase
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end
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// Memory Interface
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reg [1:0] mem_state;
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@ -334,7 +392,7 @@ module picorv32 #(
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end
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if (decoder_trigger && !decoder_pseudo_trigger) begin
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if (ENABLE_PCPI) begin
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if (WITH_PCPI) begin
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pcpi_insn <= mem_rdata_q;
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end
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@ -512,8 +570,8 @@ module picorv32 #(
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reg_alu_out <= alu_out;
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if (ENABLE_PCPI) begin
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if (pcpi_insn_valid && !pcpi_wait) begin
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if (WITH_PCPI) begin
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if (pcpi_insn_valid && !pcpi_int_wait) begin
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if (pcpi_timeout_counter)
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pcpi_timeout_counter <= pcpi_timeout_counter - 1;
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end else
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@ -602,7 +660,7 @@ module picorv32 #(
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reg_pc <= current_pc;
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reg_next_pc <= current_pc;
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if (ENABLE_PCPI) begin
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if (WITH_PCPI) begin
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pcpi_insn_valid <= 0;
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pcpi_rs1_valid <= 0;
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pcpi_rs2_valid <= 0;
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@ -659,7 +717,7 @@ module picorv32 #(
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$display("DECODE: 0x%08x %-0s", reg_pc, instruction ? instruction : "UNKNOWN");
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`endif
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if (instr_trap) begin
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if (ENABLE_PCPI) begin
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if (WITH_PCPI) begin
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pcpi_rs1_valid <= 1;
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pcpi_insn_valid <= 1;
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reg_op1 <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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@ -667,9 +725,9 @@ module picorv32 #(
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pcpi_rs2_valid <= 1;
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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if (pcpi_ready) begin
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reg_out <= pcpi_rd;
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latched_store <= pcpi_rd_valid;
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if (pcpi_int_ready) begin
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reg_out <= pcpi_int_rd;
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latched_store <= pcpi_int_rd_valid;
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cpu_state <= cpu_state_fetch;
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end else
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if (pcpi_timeout) begin
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@ -787,11 +845,11 @@ module picorv32 #(
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`endif
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reg_sh <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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reg_op2 <= decoded_rs2 ? cpuregs[decoded_rs2] : 0;
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if (ENABLE_PCPI && pcpi_insn_valid) begin
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if (WITH_PCPI && pcpi_insn_valid) begin
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pcpi_rs2_valid <= 1;
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if (pcpi_ready) begin
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reg_out <= pcpi_rd;
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latched_store <= pcpi_rd_valid;
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if (pcpi_int_ready) begin
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reg_out <= pcpi_int_rd;
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latched_store <= pcpi_int_rd_valid;
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cpu_state <= cpu_state_fetch;
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end else
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if (pcpi_timeout) begin
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@ -1130,16 +1188,6 @@ module picorv32_axi #(
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wire mem_ready;
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wire [31:0] mem_rdata;
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wire mul_pcpi_wait;
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wire mul_pcpi_ready;
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wire mul_pcpi_rd_valid;
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wire [31:0] mul_pcpi_rd;
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wire int_pcpi_wait = mul_pcpi_wait || (pcpi_wait && ENABLE_PCPI);
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wire int_pcpi_ready = mul_pcpi_ready || (pcpi_ready && ENABLE_PCPI);
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wire int_pcpi_rd_valid = mul_pcpi_rd_valid || (pcpi_rd_valid && ENABLE_PCPI);
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wire [31:0] int_pcpi_rd = mul_pcpi_rd_valid ? mul_pcpi_rd : pcpi_rd;
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picorv32_axi_adapter axi_adapter (
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.clk (clk ),
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.resetn (resetn ),
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@ -1169,33 +1217,12 @@ module picorv32_axi #(
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.mem_rdata (mem_rdata )
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);
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generate if (ENABLE_MUL) begin
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picorv32_pcpi_mul pcpi_mul (
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.clk (clk ),
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.resetn (resetn ),
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.pcpi_insn_valid( pcpi_insn_valid),
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.pcpi_insn ( pcpi_insn ),
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.pcpi_rs1_valid ( pcpi_rs1_valid ),
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.pcpi_rs1 ( pcpi_rs1 ),
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.pcpi_rs2_valid ( pcpi_rs2_valid ),
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.pcpi_rs2 ( pcpi_rs2 ),
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.pcpi_rd_valid (mul_pcpi_rd_valid ),
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.pcpi_rd (mul_pcpi_rd ),
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.pcpi_wait (mul_pcpi_wait ),
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.pcpi_ready (mul_pcpi_ready )
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);
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end else begin
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assign mul_pcpi_rd_valid = 0;
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assign mul_pcpi_rd = 1'bx;
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assign mul_pcpi_wait = 0;
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assign mul_pcpi_ready = 0;
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end endgenerate
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picorv32 #(
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.ENABLE_COUNTERS (ENABLE_COUNTERS ),
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.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
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.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
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.ENABLE_PCPI (ENABLE_PCPI || ENABLE_MUL),
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.ENABLE_PCPI (ENABLE_PCPI ),
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.ENABLE_MUL (ENABLE_MUL ),
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.ENABLE_IRQ (ENABLE_IRQ ),
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.MASKED_IRQ (MASKED_IRQ ),
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.PROGADDR_RESET (PROGADDR_RESET ),
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@ -1213,16 +1240,16 @@ module picorv32_axi #(
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.mem_ready(mem_ready),
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.mem_rdata(mem_rdata),
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.pcpi_insn_valid( pcpi_insn_valid),
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.pcpi_insn ( pcpi_insn ),
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.pcpi_rs1_valid ( pcpi_rs1_valid ),
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.pcpi_rs1 ( pcpi_rs1 ),
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.pcpi_rs2_valid ( pcpi_rs2_valid ),
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.pcpi_rs2 ( pcpi_rs2 ),
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.pcpi_rd_valid (int_pcpi_rd_valid ),
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.pcpi_rd (int_pcpi_rd ),
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.pcpi_wait (int_pcpi_wait ),
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.pcpi_ready (int_pcpi_ready ),
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.pcpi_insn_valid(pcpi_insn_valid),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1_valid (pcpi_rs1_valid ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2_valid (pcpi_rs2_valid ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_rd_valid (pcpi_rd_valid ),
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.pcpi_rd (pcpi_rd ),
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.pcpi_wait (pcpi_wait ),
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.pcpi_ready (pcpi_ready ),
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.irq(irq),
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.eoi(eoi)
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