Add rs232 decode to picosoc hx8kdemo test bench

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-08-14 14:27:09 +02:00
parent 28d6f97b00
commit 4c1e0f47a6
1 changed files with 39 additions and 0 deletions

View File

@ -23,6 +23,9 @@ module testbench;
reg clk;
always #5 clk = (clk === 1'b0);
localparam ser_half_period = 53;
event ser_sample;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
@ -34,8 +37,17 @@ module testbench;
$finish;
end
integer cycle_cnt = 0;
always @(posedge clk) begin
cycle_cnt <= cycle_cnt + 1;
end
wire [7:0] leds;
wire ser_rx;
wire ser_tx;
wire flash_csb;
wire flash_clk;
wire flash_io0;
@ -50,6 +62,8 @@ module testbench;
hx8kdemo uut (
.clk (clk ),
.leds (leds ),
.ser_rx (ser_rx ),
.ser_tx (ser_tx ),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
@ -66,4 +80,29 @@ module testbench;
.io2(flash_io2),
.io3(flash_io3)
);
reg [7:0] buffer;
always begin
@(negedge ser_tx);
repeat (ser_half_period) @(posedge clk);
-> ser_sample; // start bit
repeat (8) begin
repeat (ser_half_period) @(posedge clk);
repeat (ser_half_period) @(posedge clk);
buffer = {ser_tx, buffer[7:1]};
-> ser_sample; // data bit
end
repeat (ser_half_period) @(posedge clk);
repeat (ser_half_period) @(posedge clk);
-> ser_sample; // stop bit
if (buffer < 32 || buffer >= 127)
$display("Serial data: %d", buffer);
else
$display("Serial data: '%c'", buffer);
end
endmodule