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README.md
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README.md
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@ -91,16 +91,22 @@ This Verilog file contains the following Verilog modules:
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| `picorv32` | The PicoRV32 CPU |
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| `picorv32_axi` | The version of the CPU with AXI4-Lite interface |
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| `picorv32_axi_adapter` | Adapter from PicoRV32 Memory Interface to AXI4-Lite |
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| `picorv32_wb` | The version of the CPU with Wishbone Master interface |
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| `picorv32_pcpi_mul` | A PCPI core that implements the `MUL[H[SU|U]]` instructions |
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| `picorv32_pcpi_fast_mul` | A version of `picorv32_pcpi_fast_mul` using a single cycle multiplier |
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| `picorv32_pcpi_div` | A PCPI core that implements the `DIV[U]/REM[U]` instructions |
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Simply copy this file into your project.
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#### Makefile and testbench.v
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#### Makefile and testbenches
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A basic test environment. Run `make test`, `make test_sp` and/or `make test_axi` to run
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the test firmware in different hardware configurations.
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A basic test environment. Run `make test` to run the standard test bench (`testbench.v`)
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in the standard configurations. There are other test benches and configurations. See
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the `test_*` make target in the Makefile for details.
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Run `make test_ez` to run `testbench_ez.v`, a very simple test bench that does
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not require an external firmware .hex file. This can be useful in environments
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where the RISC-V compiler toolchain is not available.
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*Note: The test bench is using Icarus Verilog. However, Icarus Verilog 0.9.7
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(the latest release at the time of writing) has a few bugs that prevent the
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