Added scripts/yosys-cmp/

scripts/yosys-cmp/README.md

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+
+Synthesis results for the PicoRV32 core (in its default configuration) with Yosys 0.5+383 (git sha1 8648089), Synplify Pro and Lattice LSE from iCEcube2.2014.08, and Xilinx Vivado 2015.3.
+
+No timing contraints where used for synthesis; only resource utilisation is compared.
+
+Last updated: 2015-10-30
+
+
+Results for iCE40 Synthesis
+---------------------------
+
+| Cell          | Yosys | Synplify Pro | Lattice LSE |
+|:--------------|------:|-------------:|------------:|
+| `SB_CARRY`    |   405 |          349 |         309 |
+| `SB_DFF`      |   125 |          256 |         114 |
+| `SB_DFFE`     |   251 |          268 |          76 |
+| `SB_DFFESR`   |   172 |           39 |         147 |
+| `SB_DFFESS`   |     1 |            0 |          69 |
+| `SB_DFFSR`    |    69 |          137 |         134 |
+| `SB_DFFSS`    |     0 |            0 |          36 |
+| `SB_LUT4`     |  1795 |         1657 |        1621 |
+| `SB_RAM40_4K` |     4 |            4 |           4 |
+
+Summary:
+
+| Cell          | Yosys | Synplify Pro | Lattice LSE |
+|:--------------|------:|-------------:|------------:|
+| `SB_CARRY`    |   405 |          349 |         309 |
+| `SB_DFF*`     |   618 |          700 |         576 |
+| `SB_LUT4`     |  1795 |         1657 |        1621 |
+| `SB_RAM40_4K` |     4 |            4 |           4 |
+
+
+Results for Xilinx 7-Series Synthesis
+-------------------------------------
+
+| Cell        | Yosys | Vivado |
+|:------------|------:|-------:|
+| `FDRE`      |   671 |    553 |
+| `FDSE`      |     0 |     21 |
+| `LUT1`      |    41 |    160 |
+| `LUT2`      |   517 |    122 |
+| `LUT3`      |    77 |    120 |
+| `LUT4`      |   136 |    204 |
+| `LUT5`      |   142 |    135 |
+| `LUT6`      |   490 |    405 |
+| `MUXF7`     |    54 |      0 |
+| `MUXF8`     |    15 |      0 |
+| `MUXCY`     |   420 |      0 |
+| `XORCY`     |   359 |      0 |
+| `CARRY4`    |     0 |     83 |
+| `RAMD32`    |     0 |     72 |
+| `RAMS32`    |     0 |     24 |
+| `RAM64X1D`  |    64 |      0 |
+
+Summary:
+
+| Cell        | Yosys | Vivado |
+|:------------|------:|-------:|
+| `FD*`       |   671 |    574 |
+| `LUT*`      |  1403 |   1146 |
+

scripts/yosys-cmp/lse.sh

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+#!/bin/bash
+
+set -ex
+
+rm -rf lse.tmp
+mkdir lse.tmp
+cd lse.tmp
+
+cat > lse.prj << EOT
+#device
+-a SBTiCE40
+-d iCE40HX8K
+-t CT256
+#constraint file
+
+#options
+-frequency 200
+-optimization_goal Area
+-twr_paths 3
+-bram_utilization 100.00
+-ramstyle Auto
+-romstyle Auto
+-use_carry_chain 1
+-carry_chain_length 0
+-resource_sharing 1
+-propagate_constants 1
+-remove_duplicate_regs 1
+-max_fanout 10000
+-fsm_encoding_style Auto
+-use_io_insertion 1
+-use_io_reg auto
+-ifd 
+-resolve_mixed_drivers 0
+-RWCheckOnRam 0
+-fix_gated_clocks 1
+-top picorv32
+
+-ver "../../../picorv32.v"
+-p "."
+
+#set result format/file last
+-output_edif output.edf
+
+#set log file
+-logfile "lse.log"
+EOT
+
+icecubedir="${ICECUBEDIR:-/opt/lscc/iCEcube2.2014.08}"
+export FOUNDRY="$icecubedir/LSE"
+export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/LSE/bin/lin"
+"$icecubedir"/LSE/bin/lin/synthesis -f lse.prj
+
+grep 'viewRef.*cellRef' output.edf | sed 's,.*cellRef *,,; s,[ )].*,,;' | sort | uniq -c

scripts/yosys-cmp/synplify.sh

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+#!/bin/bash
+
+set -ex
+
+rm -rf synplify.tmp
+mkdir synplify.tmp
+cd synplify.tmp
+
+cat > impl_syn.prj << EOT
+add_file -verilog -lib work ../../../picorv32.v
+impl -add impl -type fpga
+
+# implementation attributes
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+
+# device options
+set_option -technology SBTiCE40
+set_option -part iCE40HX8K
+set_option -package CT256
+set_option -speed_grade
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -top_module "picorv32"
+
+# mapper_options
+set_option -frequency auto
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+# Silicon Blue iCE40
+set_option -maxfan 10000
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -retiming 0
+set_option -update_models_cp 0
+set_option -fixgatedclocks 2
+set_option -fixgeneratedclocks 0
+
+# NFilter
+set_option -popfeed 0
+set_option -constprop 0
+set_option -createhierarchy 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+# set result format/file last
+project -result_format edif
+project -result_file impl.edf
+impl -active impl
+project -run synthesis -clean
+EOT
+
+icecubedir="${ICECUBEDIR:-/opt/lscc/iCEcube2.2014.08}"
+export SBT_DIR="$icecubedir/sbt_backend"
+export SYNPLIFY_PATH="$icecubedir/synpbase"
+export LM_LICENSE_FILE="$icecubedir/license.dat"
+export TCL_LIBRARY="$icecubedir/sbt_backend/bin/linux/lib/tcl8.4"
+export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/sbt_backend/bin/linux/opt"
+export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/sbt_backend/bin/linux/opt/synpwrap"
+export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/sbt_backend/lib/linux/opt"
+export LD_LIBRARY_PATH="$LD_LIBRARY_PATH${LD_LIBRARY_PATH:+:}$icecubedir/LSE/bin/lin"
+"$icecubedir"/sbt_backend/bin/linux/opt/synpwrap/synpwrap -prj impl_syn.prj -log impl.srr
+
+grep 'instance.*cellRef' impl/impl.edf | sed 's,.*cellRef *,,; s,[ )].*,,;' | sort | uniq -c

scripts/yosys-cmp/vivado.tcl

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+read_verilog ../../picorv32.v
+synth_design -part xc7k70t-fbg676 -top picorv32
+report_utilization

scripts/yosys-cmp/yosys_ice40.ys

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+read_verilog ../../picorv32.v
+synth_ice40 -top picorv32

scripts/yosys-cmp/yosys_xilinx.ys

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+read_verilog ../../picorv32.v
+synth_xilinx -top picorv32