Hardware
/
picorv32
mirror of https://github.com/YosysHQ/picorv32.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Updated riscv-gnu-toolchain

This commit is contained in:
Clifford Wolf 2016-01-21 11:39:24 +01:00
parent d2e20edaab
commit 56ea35cc22
1 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
README.md
View File

@ -257,10 +257,10 @@ Unless stated otherwise, the following numbers apply to a PicoRV32 with
ENABLE_REGS_DUALPORT active and connected to a memory that can accommodate ENABLE_REGS_DUALPORT active and connected to a memory that can accommodate
requests within one clock cycle. requests within one clock cycle.
The average Cycles per Instruction (CPI) is 4 to 5, depending on the mix of The average Cycles per Instruction (CPI) is approximately 4, depending on the mix of
instructions in the code. The CPI numbers for the individual instructions instructions in the code. The CPI numbers for the individual instructions can
can be found in the table below. The column "CPI (SP)" contains the be found in the table below. The column "CPI (SP)" contains the CPI numbers for
CPI numbers for a core built without ENABLE_REGS_DUALPORT. a core built without ENABLE_REGS_DUALPORT.
| Instruction | CPI | CPI (SP) | | Instruction | CPI | CPI (SP) |
| ---------------------| ----:| --------:| | ---------------------| ----:| --------:|
@ -277,9 +277,9 @@ CPI numbers for a core built without ENABLE_REGS_DUALPORT.
When `ENABLE_MUL` is activated, then a `MUL` instruction will execute When `ENABLE_MUL` is activated, then a `MUL` instruction will execute
in 40 cycles and a `MULH[SU|U]` instruction will execute in 72 cycles. in 40 cycles and a `MULH[SU|U]` instruction will execute in 72 cycles.
Dhrystone benchmark results: 0.311 DMIPS/MHz (547 Dhrystones/Second/MHz) Dhrystone benchmark results: 0.327 DMIPS/MHz (575 Dhrystones/Second/MHz)
For the Dhrystone benchmark the average CPI is 4.144. For the Dhrystone benchmark the average CPI is 3.945.
PicoRV32 Native Memory Interface PicoRV32 Native Memory Interface
@ -531,7 +531,7 @@ pure RV32I target, and install it in `/opt/riscv32i`:
git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
cd riscv-gnu-toolchain-rv32i cd riscv-gnu-toolchain-rv32i
git checkout 4bcd4f5 git checkout 06c957a
mkdir build; cd build mkdir build; cd build
../configure --with-xlen=32 --with-arch=I --prefix=/opt/riscv32i ../configure --with-xlen=32 --with-arch=I --prefix=/opt/riscv32i
@ -541,7 +541,7 @@ The commands will all be named using the prefix `riscv32-unknown-elf-`, which
makes it easy to install them side-by-side with the regular riscv-tools, which makes it easy to install them side-by-side with the regular riscv-tools, which
are using the name prefix `riscv64-unknown-elf-` by default. are using the name prefix `riscv64-unknown-elf-` by default.
*Note: This instructions are for git rev 4bcd4f5 (2015-12-14) of riscv-gnu-toolchain.* *Note: This instructions are for git rev 06c957a (2016-01-20) of riscv-gnu-toolchain.*
Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs