mirror of https://github.com/YosysHQ/picorv32.git
Added more asserts for the memory interface
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2
Makefile
2
Makefile
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@ -23,7 +23,7 @@ check: check-yices
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check-%: check.smt2
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yosys-smtbmc -s $(subst check-,,$@) -t 30 --dump-vcd check.vcd check.smt2
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yosys-smtbmc -s $(subst check-,,$@) -t 20 --dump-vcd check.vcd -i check.smt2
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yosys-smtbmc -s $(subst check-,,$@) -t 25 --dump-vcd check.vcd -i check.smt2
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check.smt2: picorv32.v
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yosys -v2 -p 'read_verilog -formal picorv32.v' \
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37
picorv32.v
37
picorv32.v
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@ -470,7 +470,7 @@ module picorv32 #(
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end
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always @(posedge clk) begin
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if (resetn) begin
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if (resetn && !trap) begin
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if (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
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`assert(!mem_do_wdata);
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@ -490,7 +490,8 @@ module picorv32 #(
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always @(posedge clk) begin
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if (!resetn || trap) begin
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mem_state <= 0;
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if (!resetn)
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mem_state <= 0;
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if (!resetn || mem_ready)
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mem_valid <= 0;
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mem_la_secondword <= 0;
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@ -1795,6 +1796,9 @@ module picorv32 #(
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// resetn low in first cycle, after that resetn high
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restrict property (resetn != $initstate);
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// this just makes it much easier to read traces. uncomment as needed.
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// assume property (mem_valid || !mem_ready);
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reg ok;
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always @* begin
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if (resetn) begin
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@ -1815,6 +1819,35 @@ module picorv32 #(
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assert (ok);
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end
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end
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reg last_mem_la_read = 0;
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reg last_mem_la_write = 0;
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reg [31:0] last_mem_la_addr;
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reg [31:0] last_mem_la_wdata;
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reg [3:0] last_mem_la_wstrb = 0;
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always @(posedge clk) begin
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last_mem_la_read <= mem_la_read;
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last_mem_la_write <= mem_la_write;
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last_mem_la_addr <= mem_la_addr;
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last_mem_la_wdata <= mem_la_wdata;
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last_mem_la_wstrb <= mem_la_wstrb;
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if (last_mem_la_read) begin
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assert(mem_valid);
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assert(mem_addr == last_mem_la_addr);
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assert(mem_wstrb == 0);
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end
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if (last_mem_la_write) begin
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assert(mem_valid);
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assert(mem_addr == last_mem_la_addr);
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assert(mem_wdata == last_mem_la_wdata);
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assert(mem_wstrb == last_mem_la_wstrb);
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end
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if (mem_la_read || mem_la_write) begin
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assert(!mem_valid || mem_ready);
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end
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end
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`endif
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endmodule
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