mirror of https://github.com/YosysHQ/picorv32.git
Implemented waitirq instruction
This commit is contained in:
Clifford Wolf
parent
9a4a06d981
commit
5d4ce82050
37
README.md
37
README.md
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@ -164,10 +164,10 @@ when saving/restoring register values in the IRQ handler.
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#### getq rd, qs
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This instruction copies the value from a q-register to a general-purpose
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register. The Instruction is encoded under the `custom0` opcode:
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register. This instruction is encoded under the `custom0` opcode:
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0000000 00000 000XX 000 XXXXX 0001011
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f7 f5 qs f3 rd opcode
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f7 rs2 qs f3 rd opcode
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Example assembler code using the `custom0` mnemonic:
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@ -180,10 +180,10 @@ Example assembler code using the `custom0` mnemonic:
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#### setq qd, rs
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This instruction copies the value from a general-purpose register to a
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q-register. The Instruction is encoded under the `custom0` opcode:
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q-register. This instruction is encoded under the `custom0` opcode:
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0000001 00000 XXXXX 000 000XX 0001011
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f7 f5 rs f3 qd opcode
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f7 rs2 rs f3 qd opcode
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Example assembler code using the `custom0` mnemonic:
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@ -196,11 +196,11 @@ Example assembler code using the `custom0` mnemonic:
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#### retirq
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Return from interrupt. This instruction copies the value from `q0`
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to the program counter and re-enables interrupts. The Instruction is
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to the program counter and re-enables interrupts. This instruction is
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encoded under the `custom0` opcode:
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0000010 00000 00000 000 00000 0001011
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f7 f5 rs f3 rd opcode
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f7 rs2 rs f3 rd opcode
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Example assembler code using the `custom0` mnemonic:
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@ -214,11 +214,11 @@ The "IRQ Mask" register contains a birtmask of masked (disabled) interrupts.
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This opcodes writes a new value to the irq mask register and reads the old
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value.
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Enable/disable interrupt sources. The Instruction is encoded under the
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Enable/disable interrupt sources. This instruction is encoded under the
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`custom0` opcode:
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0000011 00000 XXXXX 000 XXXXX 0001011
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f7 f5 rs f3 rd opcode
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f7 rs2 rs f3 rd opcode
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Example assembler code using the `custom0` mnemonic:
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@ -231,34 +231,35 @@ The processor starts with all interrupts disabled.
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An illegal instruction or bus error while the illegal instruction or bus error
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interrupt is disabled will cause the processor to halt.
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#### waitirq (unimplemented)
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#### waitirq
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Pause execution until an interrupt triggers. The Instruction is encoded under the
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`custom0` opcode:
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Pause execution until an interrupt triggers. This instruction is encoded under the
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`custom0` opcode. The bitmask of pending IRQs is written to `rd`.
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0000100 00000 00000 000 00000 0001011
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f7 f5 rs f3 rd opcode
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0000100 00000 00000 000 XXXXX 0001011
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f7 rs2 rs f3 rd opcode
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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| waitirq | custom0 0, 0, 0, 4 |
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| waitirq x1 | custom0 1, 0, 0, 4 |
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#### timer
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Reset the timer counter to a new value. The counter counts down clock cycles and
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triggers the timer interrupt when transitioning from 1 to 0. Setting the
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counter to zero disables the timer.
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counter to zero disables the timer. The old value of the counter is written to
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`rd`.
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0000101 00000 XXXXX 000 00000 0001011
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f7 f5 rs f3 rd opcode
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0000101 00000 XXXXX 000 XXXXX 0001011
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f7 rs2 rs f3 rd opcode
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Example assembler code using the `custom0` mnemonic:
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| Instruction | Assember Code |
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| ------------------| --------------------|
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| timer x2 | custom0 0, 2, 0, 5 |
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| timer x1, x2 | custom0 1, 2, 0, 5 |
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Todos:
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@ -6,10 +6,11 @@
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#define TEST(n) \
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.global n; .global n ## _ret; \
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addi x1, zero, 1000; \
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custom0 0,1,0,5; /* timer x1 */ \
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custom0 0,1,0,5; /* timer zero, x1 */ \
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jal zero,n; n ## _ret:
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reset_vec:
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custom0 0,0,0,4 // waitirq zero
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custom0 0,0,0,3 // maskirq zero, zero
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j start
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nop
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30
picorv32.v
30
picorv32.v
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@ -291,12 +291,12 @@ module picorv32 #(
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is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
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if (mem_do_rinst && mem_done) begin
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instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
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instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
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instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
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instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111;
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instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
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instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
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instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
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instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
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instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111;
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instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
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instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;
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is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
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is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011;
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@ -367,7 +367,6 @@ module picorv32 #(
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instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ;
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instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ;
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instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
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instr_waitirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000100 && ENABLE_IRQ;
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instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ;
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is_slli_srli_srai <= is_alu_reg_imm && |{
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@ -439,6 +438,7 @@ module picorv32 #(
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assign next_pc = latched_store && latched_branch ? reg_out : reg_next_pc;
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reg [31:0] next_irq_pending;
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reg do_waitirq;
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reg [31:0] alu_out;
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reg alu_out_0;
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@ -507,6 +507,7 @@ module picorv32 #(
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decoder_trigger_q <= decoder_trigger;
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decoder_trigger <= mem_do_rinst && mem_done;
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decoder_pseudo_trigger <= 0;
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do_waitirq <= 0;
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if (!resetn) begin
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reg_pc <= PROGADDR_RESET;
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@ -533,7 +534,7 @@ module picorv32 #(
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trap <= 1;
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end
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cpu_state_fetch: begin
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mem_do_rinst <= !decoder_trigger;
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mem_do_rinst <= !decoder_trigger && !do_waitirq;
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mem_wordsize <= 0;
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current_pc = reg_next_pc;
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@ -580,6 +581,15 @@ module picorv32 #(
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irq_state == 2'b01 ? 2'b10 : 2'b00;
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latched_rd <= irqregs_offset | irq_state[0];
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end else
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if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
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if (irq_pending) begin
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latched_store <= 1;
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reg_out <= irq_pending;
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reg_next_pc <= current_pc + 4;
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mem_do_rinst <= 1;
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end else
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do_waitirq <= 1;
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end else
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if (decoder_trigger) begin
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`ifdef DEBUG
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$display("-- %-0t", $time);
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@ -664,7 +674,9 @@ module picorv32 #(
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cpu_state <= cpu_state_fetch;
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end else
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if (ENABLE_IRQ && instr_timer) begin
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timer <= cpuregs[decoded_rs1];
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latched_store <= 1;
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reg_out <= timer;
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timer <= decoded_rs1 ? cpuregs[decoded_rs1] : 0;
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cpu_state <= cpu_state_fetch;
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end else begin
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`ifdef DEBUG
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