mirror of https://github.com/YosysHQ/picorv32.git
Towards compressed ISA support
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Clifford Wolf
parent
db26b51afe
commit
60b9216856
44
picorv32.v
44
picorv32.v
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@ -180,15 +180,22 @@ module picorv32 #(
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reg mem_do_rdata;
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reg mem_do_wdata;
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reg mem_la_secondword;
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wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
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reg [15:0] mem_16bit_buffer;
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wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
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wire mem_done = resetn && ((mem_ready && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst));
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wire mem_done = resetn && ((mem_ready && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) && !mem_la_firstword;
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assign mem_la_write = resetn && !mem_state && mem_do_wdata;
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assign mem_la_read = resetn && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata);
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assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2], 2'b00} : {reg_op1[31:2], 2'b00};
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assign mem_la_read = resetn && ((!mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) || (mem_ready && mem_la_firstword && !mem_la_secondword));
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assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + (mem_ready && mem_la_firstword), 2'b00} : {reg_op1[31:2], 2'b00};
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wire [31:0] mem_rdata_latched_noshuffle;
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assign mem_rdata_latched_noshuffle = ((mem_valid && mem_ready) || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
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wire [31:0] mem_rdata_latched;
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assign mem_rdata_latched = ((mem_valid && mem_ready) || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
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assign mem_rdata_latched = COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} : mem_rdata_latched_noshuffle;
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always @* begin
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(* full_case *)
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@ -221,7 +228,7 @@ module picorv32 #(
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always @(posedge clk) begin
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if (mem_valid && mem_ready) begin
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mem_rdata_q <= mem_rdata_latched;
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mem_rdata_q <= mem_rdata;
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if (COMPRESSED_ISA && mem_do_rinst) begin
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case (mem_rdata_latched[1:0] == 1)
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@ -253,6 +260,7 @@ module picorv32 #(
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if (!resetn) begin
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mem_state <= 0;
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mem_valid <= 0;
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mem_la_secondword <= 0;
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end else case (mem_state)
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0: begin
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mem_addr <= mem_la_addr;
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@ -272,8 +280,15 @@ module picorv32 #(
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end
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1: begin
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if (mem_ready) begin
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mem_valid <= 0;
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mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
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if (COMPRESSED_ISA && mem_la_firstword && !mem_la_secondword) begin
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mem_addr <= mem_la_addr;
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mem_la_secondword <= 1;
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mem_16bit_buffer <= mem_rdata[31:16];
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end else begin
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mem_valid <= 0;
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mem_la_secondword <= 0;
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mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
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end
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end
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end
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2: begin
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@ -303,7 +318,7 @@ module picorv32 #(
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wire instr_trap;
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reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
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reg [31:0] decoded_imm, decoded_imm_uj;
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reg [31:0] decoded_imm, decoded_imm_uj, current_insn;
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reg decoder_trigger;
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reg decoder_trigger_q;
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reg decoder_pseudo_trigger;
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@ -340,6 +355,7 @@ module picorv32 #(
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always @(posedge clk) begin
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new_ascii_instr = "";
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if (instr_lui) new_ascii_instr = "lui";
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if (instr_auipc) new_ascii_instr = "auipc";
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if (instr_jal) new_ascii_instr = "jal";
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@ -394,8 +410,10 @@ module picorv32 #(
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if (instr_waitirq) new_ascii_instr = "waitirq";
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if (instr_timer) new_ascii_instr = "timer";
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if (decoder_trigger_q)
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if (decoder_trigger_q) begin
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ascii_instr <= new_ascii_instr;
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`debug($display("DECODE: 0x%08x 0x%08x %-0s", reg_pc, current_insn, new_ascii_instr ? new_ascii_instr : "UNKNOWN");)
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end
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end
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always @(posedge clk) begin
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@ -407,6 +425,8 @@ module picorv32 #(
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is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
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if (mem_do_rinst && mem_done) begin
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current_insn <= mem_rdata_latched;
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instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
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instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
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instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
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@ -810,7 +830,6 @@ module picorv32 #(
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if (ENABLE_COUNTERS)
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count_instr <= count_instr + 1;
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if (instr_jal) begin
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`debug($display("DECODE: 0x%08x jal", current_pc);)
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mem_do_rinst <= 1;
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reg_next_pc <= current_pc + decoded_imm_uj;
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latched_branch <= 1;
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@ -825,7 +844,6 @@ module picorv32 #(
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cpu_state_ld_rs1: begin
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reg_op1 <= 'bx;
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reg_op2 <= 'bx;
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`debug($display("DECODE: 0x%08x %-0s", reg_pc, ascii_instr ? ascii_instr : "UNKNOWN");)
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(* parallel_case *)
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case (1'b1)
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@ -1525,6 +1543,7 @@ module picorv32_axi_adapter (
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reg ack_awvalid;
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reg ack_arvalid;
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reg ack_wvalid;
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reg xfer_done;
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assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
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assign mem_axi_awaddr = mem_addr;
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@ -1547,13 +1566,14 @@ module picorv32_axi_adapter (
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if (!resetn) begin
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ack_awvalid <= 0;
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end else begin
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xfer_done <= mem_valid && mem_ready;
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if (mem_axi_awready && mem_axi_awvalid)
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ack_awvalid <= 1;
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if (mem_axi_arready && mem_axi_arvalid)
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ack_arvalid <= 1;
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if (mem_axi_wready && mem_axi_wvalid)
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ack_wvalid <= 1;
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if (!mem_valid) begin
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if (xfer_done || !mem_valid) begin
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ack_awvalid <= 0;
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ack_arvalid <= 0;
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ack_wvalid <= 0;
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