mirror of https://github.com/YosysHQ/picorv32.git
Added mem timing variations to scripts/csmith/ testbench
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@ -34,6 +34,19 @@ module testbench (
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wire [3:0] mem_wstrb;
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wire [31:0] mem_rdata;
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reg [31:0] x32 = 314159265;
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reg [31:0] next_x32;
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always @(posedge clk) begin
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if (resetn) begin
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next_x32 = x32;
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next_x32 = next_x32 ^ (next_x32 << 13);
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next_x32 = next_x32 ^ (next_x32 >> 17);
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next_x32 = next_x32 ^ (next_x32 << 5);
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x32 <= next_x32;
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end
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end
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picorv32 #(
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.COMPRESSED_ISA(1),
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.ENABLE_MUL(1),
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@ -54,7 +67,7 @@ module testbench (
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reg [7:0] memory [0:4*1024*1024-1];
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initial $readmemh("test.hex", memory);
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assign mem_ready = 1;
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assign mem_ready = x32[0] && mem_valid;
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assign mem_rdata[ 7: 0] = memory[mem_addr + 0];
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assign mem_rdata[15: 8] = memory[mem_addr + 1];
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@ -62,16 +75,18 @@ module testbench (
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assign mem_rdata[31:24] = memory[mem_addr + 3];
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always @(posedge clk) begin
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if (mem_valid && mem_wstrb && mem_addr == 'h10000000) begin
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$write("%c", mem_wdata[ 7: 0]);
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if (mem_valid && mem_ready) begin
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if (mem_wstrb && mem_addr == 'h10000000) begin
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$write("%c", mem_wdata[ 7: 0]);
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`ifndef VERILATOR
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$fflush;
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$fflush;
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`endif
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end else begin
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if (mem_valid && mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
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if (mem_valid && mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
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if (mem_valid && mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16];
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if (mem_valid && mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24];
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end else begin
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if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24];
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end
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end
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end
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