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Using fast mul in dhrystone benchmark

This commit is contained in:
Clifford Wolf 2016-08-30 11:24:04 +02:00
parent dc9b100814
commit 6af226a385
2 changed files with 3 additions and 4 deletions
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6
README.md
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@ -345,11 +345,11 @@ When `BARREL_SHIFTER` is activated, a shift operation takes as long as
any other ALU operation.
The following dhrystone benchmark results are for a core with enabled
`ENABLE_MUL`, `ENABLE_DIV`, and `BARREL_SHIFTER` options.
`ENABLE_FAST_MUL`, `ENABLE_DIV`, and `BARREL_SHIFTER` options.
Dhrystone benchmark results: 0.505 DMIPS/MHz (888 Dhrystones/Second/MHz)
Dhrystone benchmark results: 0.521 DMIPS/MHz (916 Dhrystones/Second/MHz)
For the Dhrystone benchmark the average CPI is 4.208.
For the Dhrystone benchmark the average CPI is 4.081.
PicoRV32 Native Memory Interface

1
dhrystone/testbench.v
View File

@ -28,7 +28,6 @@ module testbench;
picorv32 #(
.BARREL_SHIFTER(1),
.ENABLE_MUL(1),
.ENABLE_FAST_MUL(1),
.ENABLE_DIV(1),
.PROGADDR_RESET('h10000),