mirror of https://github.com/YosysHQ/picorv32.git
Using .vvp instead of .exe for iverilog executables
This commit is contained in:
parent
84bd9e9b88
commit
6c69b3812e
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@ -8,9 +8,9 @@
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/dhrystone/dhry.elf
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/dhrystone/dhry.hex
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/dhrystone/dhry.map
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/dhrystone/testbench.exe
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/dhrystone/testbench.vvp
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/dhrystone/testbench.vcd
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/dhrystone/timing.exe
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/dhrystone/timing.vvp
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/dhrystone/timing.txt
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/dhrystone/*.d
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/dhrystone/*.o
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@ -18,10 +18,9 @@
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/riscv-gnu-toolchain-riscv32ic
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/riscv-gnu-toolchain-riscv32im
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/riscv-gnu-toolchain-riscv32imc
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/testbench.exe
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/testbench_sp.exe
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/testbench_axi.exe
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/testbench_synth.exe
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/testbench.vvp
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/testbench_sp.vvp
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/testbench_synth.vvp
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/testbench.gtkw
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/testbench.vcd
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/check.smt2
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38
Makefile
38
Makefile
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@ -11,10 +11,10 @@ GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedanti
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TOOLCHAIN_PREFIX = /opt/riscv32i/bin/riscv32-unknown-elf-
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COMPRESSED_ISA = C
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test: testbench.exe firmware/firmware.hex
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vvp -N testbench.exe
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test: testbench.vvp firmware/firmware.hex
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vvp -N testbench.vvp
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testbench.vcd: testbench.exe firmware/firmware.hex
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testbench.vcd: testbench.vvp firmware/firmware.hex
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vvp -N $< +vcd
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view: testbench.vcd
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@ -29,26 +29,26 @@ check.smt2: picorv32.v
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-p 'prep -top picorv32 -nordff' \
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-p 'write_smt2 -bv -mem -wires check.smt2'
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test_sp: testbench_sp.exe firmware/firmware.hex
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vvp -N testbench_sp.exe
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test_sp: testbench_sp.vvp firmware/firmware.hex
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vvp -N testbench_sp.vvp
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test_axi: testbench.exe firmware/firmware.hex
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vvp -N testbench.exe +axi_test
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test_axi: testbench.vvp firmware/firmware.hex
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vvp -N testbench.vvp +axi_test
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test_synth: testbench_synth.exe firmware/firmware.hex
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vvp -N testbench_synth.exe
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test_synth: testbench_synth.vvp firmware/firmware.hex
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vvp -N testbench_synth.vvp
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testbench.exe: testbench.v picorv32.v
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iverilog -o testbench.exe $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) testbench.v picorv32.v
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chmod -x testbench.exe
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testbench.vvp: testbench.v picorv32.v
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iverilog -o testbench.vvp $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) testbench.v picorv32.v
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chmod -x testbench.vvp
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testbench_sp.exe: testbench.v picorv32.v
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iverilog -o testbench_sp.exe $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DSP_TEST testbench.v picorv32.v
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chmod -x testbench_sp.exe
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testbench_sp.vvp: testbench.v picorv32.v
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iverilog -o testbench_sp.vvp $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DSP_TEST testbench.v picorv32.v
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chmod -x testbench_sp.vvp
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testbench_synth.exe: testbench.v synth.v
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iverilog -o testbench_synth.exe testbench.v synth.v
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chmod -x testbench_synth.exe
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testbench_synth.vvp: testbench.v synth.v
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iverilog -o testbench_synth.vvp testbench.v synth.v
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chmod -x testbench_synth.vvp
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synth.v: picorv32.v scripts/yosys/synth_sim.ys
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yosys -qv3 -l synth.log scripts/yosys/synth_sim.ys
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@ -119,7 +119,7 @@ clean:
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riscv-gnu-toolchain-riscv32im riscv-gnu-toolchain-riscv32imc
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rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) check.smt2 check.vcd synth.v synth.log \
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firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
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testbench.exe testbench_sp.exe testbench_synth.exe testbench.vcd
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testbench.vvp testbench_sp.vvp testbench_synth.vvp testbench.vcd
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.PHONY: test view test_sp test_axi test_synth download-tools toc clean
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@ -3,23 +3,23 @@ OBJS = start.o dhry_1.o dhry_2.o stdlib.o
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CFLAGS = -MD -O3 -m32 -march=RV32IM -ffreestanding -nostdlib -DTIME -DRISCV
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TOOLCHAIN_PREFIX = riscv32-unknown-elf-
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test: testbench.exe dhry.hex
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vvp -N testbench.exe
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test: testbench.vvp dhry.hex
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vvp -N testbench.vvp
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timing: timing.txt
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grep '^##' timing.txt | gawk 'x != "" {print x,$$3-y;} {x=$$2;y=$$3;}' | sort | uniq -c | \
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gawk '{printf("%03d-%-7s %2d %-8s (%d)\n",$$3,$$2,$$3,$$2,$$1);}' | sort | cut -c13-
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timing.txt: timing.exe dhry.hex
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vvp -N timing.exe > timing.txt
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timing.txt: timing.vvp dhry.hex
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vvp -N timing.vvp > timing.txt
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testbench.exe: testbench.v ../picorv32.v
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iverilog -o testbench.exe testbench.v ../picorv32.v
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chmod -x testbench.exe
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testbench.vvp: testbench.v ../picorv32.v
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iverilog -o testbench.vvp testbench.v ../picorv32.v
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chmod -x testbench.vvp
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timing.exe: testbench.v ../picorv32.v
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iverilog -o timing.exe -DTIMING testbench.v ../picorv32.v
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chmod -x timing.exe
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timing.vvp: testbench.v ../picorv32.v
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iverilog -o timing.vvp -DTIMING testbench.v ../picorv32.v
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chmod -x timing.vvp
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dhry.hex: dhry.bin ../firmware/makehex.py
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python3 ../firmware/makehex.py $< 16384 > $@
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@ -41,7 +41,7 @@ dhry.elf: $(OBJS) ../firmware/sections.lds
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dhry_1.o dhry_2.o: CFLAGS += -Wno-implicit-int -Wno-implicit-function-declaration
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clean:
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rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.exe testbench.vcd timing.exe timing.txt
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rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.vvp testbench.vcd timing.vvp timing.txt
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.PHONY: test clean
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@ -6,7 +6,7 @@ platform.info
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test.c
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test.ld
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test.elf
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test.exe
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test_ref
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test.hex
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testbench.exe
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testbench.vvp
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testbench.vcd
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@ -3,9 +3,9 @@ RISCV_TOOLS_PREFIX = $(RISCV_TOOLS_DIR)/bin/riscv32-unknown-elf-
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CSMITH_INCDIR = $(shell ls -d /usr/local/include/csmith-* | head -n1)
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CC = $(RISCV_TOOLS_PREFIX)gcc
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run: test.exe test.hex testbench.exe
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./test.exe | tee output_ref.txt
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vvp -N testbench.exe | tee output_sim.txt
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run: test_ref test.hex testbench.vvp
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./test_ref | tee output_ref.txt
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vvp -N testbench.vvp | tee output_sim.txt
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diff -u output_ref.txt output_sim.txt
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spike: riscv-fesvr/build.ok riscv-isa-sim/build.ok test.elf
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@ -24,9 +24,9 @@ riscv-isa-sim/build.ok: riscv-fesvr/build.ok
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cd riscv-isa-sim && LDFLAGS="-L../riscv-fesvr" ./configure --with-isa=RV32IMC
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+cd riscv-isa-sim && ln -s ../riscv-fesvr/fesvr . && make && touch build.ok
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testbench.exe: testbench.v ../../picorv32.v
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iverilog -o testbench.exe testbench.v ../../picorv32.v
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chmod -x testbench.exe
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testbench.vvp: testbench.v ../../picorv32.v
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iverilog -o testbench.vvp testbench.v ../../picorv32.v
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chmod -x testbench.vvp
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test.hex: test.elf
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$(RISCV_TOOLS_PREFIX)objcopy -O verilog test.elf test.hex
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$(CC) -nostdlib -o start.elf start.S -T start.ld
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chmod -x start.elf
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test.exe: test.c
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gcc -m32 -o test.exe -w -Os -I $(CSMITH_INCDIR) test.c
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test_ref: test.c
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gcc -m32 -o test_ref -w -Os -I $(CSMITH_INCDIR) test.c
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test.elf: test.c syscalls.c start.S
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sed -e '/SECTIONS/,+1 s/{/{ . = 0x00000000; .start : { *(.text.start) } application_entry_point = 0x00010000;/;' \
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csmith -o test.c
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clean:
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rm -f platform.info test.c test.ld test.elf test.hex test.exe
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rm -f testbench.exe testbench.vcd output_ref.txt output_sim.txt
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rm -f platform.info test.c test.ld test.elf test.hex test_ref
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rm -f testbench.vvp testbench.vcd output_ref.txt output_sim.txt
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mrproper: clean
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rm -rf riscv-fesvr riscv-isa-sim
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firmware32.hex
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firmware.o
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syscalls.o
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testbench.exe
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testbench.vvp
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testbench.vcd
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start.elf
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LDFLAGS = -Wl,--gc-sections
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LDLIBS = -lstdc++
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test: testbench.exe firmware32.hex
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vvp -N testbench.exe
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test: testbench.vvp firmware32.hex
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vvp -N testbench.vvp
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testbench.exe: testbench.v ../../picorv32.v
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iverilog -o testbench.exe testbench.v ../../picorv32.v
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chmod -x testbench.exe
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testbench.vvp: testbench.v ../../picorv32.v
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iverilog -o testbench.vvp testbench.v ../../picorv32.v
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chmod -x testbench.vvp
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firmware32.hex: firmware.elf start.elf hex8tohex32.py
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$(RISCV_TOOLS_PREFIX)objcopy -O verilog start.elf start.tmp
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clean:
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rm -f *.o *.d *.tmp start.elf
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rm -f firmware.elf firmware.hex firmware32.hex
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rm -f testbench.exe testbench.vcd
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rm -f testbench.vvp testbench.vcd
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-include *.d
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.PHONY: test clean
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example.bin: example.txt
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icepack example.txt example.bin
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example_tb.exe: example_tb.v example.v firmware.hex
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iverilog -o example_tb.exe -s testbench example.v example_tb.v ../../picorv32.v
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chmod -x example_tb.exe
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example_tb.vvp: example_tb.v example.v firmware.hex
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iverilog -o example_tb.vvp -s testbench example.v example_tb.v ../../picorv32.v
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chmod -x example_tb.vvp
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example_sim: example_tb.exe
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vvp -N example_tb.exe
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example_sim: example_tb.vvp
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vvp -N example_tb.vvp
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example_sim_vcd: example_tb.exe
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vvp -N example_tb.exe +vcd
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example_sim_vcd: example_tb.vvp
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vvp -N example_tb.vvp +vcd
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synth_tb.exe: example_tb.v synth.blif
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iverilog -o synth_tb.exe -s testbench synth.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v
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chmod -x synth_tb.exe
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synth_tb.vvp: example_tb.v synth.blif
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iverilog -o synth_tb.vvp -s testbench synth.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v
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chmod -x synth_tb.vvp
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synth_sim: synth_tb.exe
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vvp -N synth_tb.exe
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synth_sim: synth_tb.vvp
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vvp -N synth_tb.vvp
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synth_sim_vcd: synth_tb.exe
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vvp -N synth_tb.exe +vcd
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synth_sim_vcd: synth_tb.vvp
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vvp -N synth_tb.vvp +vcd
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route.v: example.txt
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icebox_vlog -L -n top -sp example.pcf example.txt > route.v
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route_tb.exe: example_tb.v route.v
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iverilog -o route_tb.exe -s testbench route.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v
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chmod -x route_tb.exe
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route_tb.vvp: example_tb.v route.v
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iverilog -o route_tb.vvp -s testbench route.v example_tb.v /usr/local/share/yosys/ice40/cells_sim.v
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chmod -x route_tb.vvp
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route_sim: route_tb.exe
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vvp -N route_tb.exe
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route_sim: route_tb.vvp
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vvp -N route_tb.vvp
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route_sim_vcd: route_tb.exe
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vvp -N route_tb.exe +vcd
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route_sim_vcd: route_tb.vvp
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vvp -N route_tb.vvp +vcd
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prog_sram:
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iceprog -S example.bin
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clean:
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rm -f firmware.elf firmware.map firmware.bin firmware.hex
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rm -f synth.log synth.v synth.blif route.v example.txt example.bin
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rm -f example_tb.exe synth_tb.exe route_tb.exe example.vcd
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rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd
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.PHONY: all prog_sram view clean
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.PHONY: example_sim synth_sim route_sim
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