mirror of https://github.com/YosysHQ/picorv32.git
Bump riscv-gnu-toolchain version
This commit is contained in:
Clifford Wolf
parent
473ff0d700
commit
6e6aeaeab6
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@ -531,7 +531,7 @@ pure RV32I target, and install it in `/opt/riscv32i`:
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git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
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cd riscv-gnu-toolchain-rv32i
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git checkout 1d8d8bc
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git checkout 4bcd4f5
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mkdir build; cd build
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../configure --with-xlen=32 --with-arch=I --prefix=/opt/riscv32i
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@ -541,7 +541,7 @@ The commands will all be named using the prefix `riscv32-unknown-elf-`, which
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makes it easy to install them side-by-side with the regular riscv-tools, which
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are using the name prefix `riscv64-unknown-elf-` by default.
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*Note: This instructions are for git rev 1d8d8bc (2015-11-21) of riscv-gnu-toolchain.*
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*Note: This instructions are for git rev 4bcd4f5 (2015-12-14) of riscv-gnu-toolchain.*
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Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs
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@ -48,11 +48,11 @@ RVTEST_CODE_BEGIN
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TEST_IMM_DEST_BYPASS( 22, 0, srl, 0x7fffc000, 0xffff8000, 1 );
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TEST_IMM_DEST_BYPASS( 23, 1, srl, 0x0003fffe, 0xffff8000, 14 );
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TEST_IMM_DEST_BYPASS( 24, 2, srl, 0x0001ffff, 0xffff8000, 15 );
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TEST_IMM_SRC1_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1 );
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TEST_IMM_SRC1_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 );
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TEST_IMM_SRC1_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 );
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TEST_IMM_ZEROSRC1( 28, srli, 0, 31 );
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TEST_IMM_ZERODEST( 29, srli, 33, 20 );
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@ -286,7 +286,7 @@ test_ ## testnum: \
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test_ ## testnum: \
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li TESTNUM, testnum; \
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li x4, 0; \
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1: la x1, result; \
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1: li x1, result; \
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TEST_INSERT_NOPS_ ## src1_nops \
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la x2, base; \
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TEST_INSERT_NOPS_ ## src2_nops \
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@ -304,7 +304,7 @@ test_ ## testnum: \
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li x4, 0; \
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1: la x2, base; \
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TEST_INSERT_NOPS_ ## src1_nops \
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la x1, result; \
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li x1, result; \
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TEST_INSERT_NOPS_ ## src2_nops \
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store_inst x1, offset(x2); \
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load_inst x3, offset(x2); \
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@ -564,129 +564,6 @@ test_ ## testnum: \
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.double result; \
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1:
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#-----------------------------------------------------------------------
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# RV64SV MACROS
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#-----------------------------------------------------------------------
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#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
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la a0, handler ## testnum; \
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csrw stvec, a0; \
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vsetcfg nxreg, nfreg; \
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li a0, 4; \
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vsetvl a0, a0; \
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la a0, src1; \
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la a1, src2; \
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vld vx2, a0; \
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vld vx3, a1; \
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lui a0,%hi(vtcode1 ## testnum); \
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vf %lo(vtcode1 ## testnum)(a0); \
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la reg2, dest; \
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illegal ## testnum: \
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inst reg1, reg2; \
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la a3, dest; \
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vsd vx2, a3; \
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fence; \
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vtcode1 ## testnum: \
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add x2, x2, x3; \
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stop; \
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vtcode2 ## testnum: \
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add x2, x2, x3; \
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stop; \
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handler ## testnum: \
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vxcptkill; \
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li TESTNUM,2; \
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csrr a0, scause; \
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li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
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bne a0,a1,fail; \
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csrr a0, sbadaddr; \
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la a1, illegal ## testnum; \
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lw a2, 0(a1); \
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bne a0, a2, fail; \
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vsetcfg 32,0; \
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li a0,4; \
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vsetvl a0,a0; \
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la a0,src1; \
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la a1,src2; \
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vld vx2,a0; \
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vld vx3,a1; \
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lui a0,%hi(vtcode2 ## testnum); \
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vf %lo(vtcode2 ## testnum)(a0); \
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la a3,dest; \
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vsd vx2,a3; \
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fence; \
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ld a1,0(a3); \
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li a2,5; \
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li TESTNUM,2; \
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bne a1,a2,fail; \
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ld a1,8(a3); \
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li TESTNUM,3; \
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bne a1,a2,fail; \
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ld a1,16(a3); \
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li TESTNUM,4; \
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bne a1,a2,fail; \
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ld a1,24(a3); \
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li TESTNUM,5; \
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bne a1,a2,fail; \
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#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
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la a0, handler ## testnum; \
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csrw stvec, a0; \
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vsetcfg nxreg, nfreg; \
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li a0, 4; \
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vsetvl a0, a0; \
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la a0, src1; \
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la a1, src2; \
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vld vx2, a0; \
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vld vx3, a1; \
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lui a0,%hi(vtcode1 ## testnum); \
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vf %lo(vtcode1 ## testnum)(a0); \
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la a3, dest; \
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vsd vx2, a3; \
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fence; \
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vtcode1 ## testnum: \
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add x2, x2, x3; \
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illegal ## testnum: \
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inst reg1, reg2, reg3; \
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stop; \
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vtcode2 ## testnum: \
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add x2, x2, x3; \
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stop; \
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handler ## testnum: \
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vxcptkill; \
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li TESTNUM,2; \
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csrr a0, scause; \
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li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
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bne a0,a1,fail; \
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csrr a0, sbadaddr; \
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la a1,illegal ## testnum; \
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bne a0,a1,fail; \
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vsetcfg 32,0; \
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li a0,4; \
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vsetvl a0,a0; \
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la a0,src1; \
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la a1,src2; \
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vld vx2,a0; \
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vld vx3,a1; \
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lui a0,%hi(vtcode2 ## testnum); \
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vf %lo(vtcode2 ## testnum)(a0); \
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la a3,dest; \
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vsd vx2,a3; \
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fence; \
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ld a1,0(a3); \
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li a2,5; \
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li TESTNUM,2; \
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bne a1,a2,fail; \
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ld a1,8(a3); \
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li TESTNUM,3; \
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bne a1,a2,fail; \
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ld a1,16(a3); \
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li TESTNUM,4; \
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bne a1,a2,fail; \
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ld a1,24(a3); \
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li TESTNUM,5; \
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bne a1,a2,fail; \
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#-----------------------------------------------------------------------
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# Pass and fail code (assumes test num is in TESTNUM)
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#-----------------------------------------------------------------------
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