Add newlib linker info to README file

This commit is contained in:
Clifford Wolf 2017-01-15 14:38:27 +01:00
parent 4e6cad88bc
commit 70f3c33ac8
2 changed files with 30 additions and 4 deletions

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@ -23,6 +23,7 @@ PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wi
- [Pico Co-Processor Interface (PCPI)](#pico-co-processor-interface-pcpi) - [Pico Co-Processor Interface (PCPI)](#pico-co-processor-interface-pcpi)
- [Custom Instructions for IRQ Handling](#custom-instructions-for-irq-handling) - [Custom Instructions for IRQ Handling](#custom-instructions-for-irq-handling)
- [Building a pure RV32I Toolchain](#building-a-pure-rv32i-toolchain) - [Building a pure RV32I Toolchain](#building-a-pure-rv32i-toolchain)
- [Linking binaries with newlib for PicoRV32](#linking-binaries-with-newlib-for-picorv32)
- [Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs](#evaluation-timing-and-utilization-on-xilinx-7-series-fpgas) - [Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs](#evaluation-timing-and-utilization-on-xilinx-7-series-fpgas)
@ -596,13 +597,18 @@ Example:
Building a pure RV32I Toolchain Building a pure RV32I Toolchain
------------------------------- -------------------------------
TL;DR: Run the following commands to build the complete toolchain:
make download-tools
make -j$(nproc) build-tools
The default settings in the [riscv-tools](https://github.com/riscv/riscv-tools) build The default settings in the [riscv-tools](https://github.com/riscv/riscv-tools) build
scripts will build a compiler, assembler and linker that can target any RISC-V ISA, scripts will build a compiler, assembler and linker that can target any RISC-V ISA,
but the libraries are built for RV32G and RV64G targets. Follow the instructions but the libraries are built for RV32G and RV64G targets. Follow the instructions
below to build a complete toolchain (including libraries) that target a pure RV32I below to build a complete toolchain (including libraries) that target a pure RV32I
CPU. CPU.
The following commands will build the RISC-V gnu toolchain and libraries for a The following commands will build the RISC-V GNU toolchain and libraries for a
pure RV32I target, and install it in `/opt/riscv32i`: pure RV32I target, and install it in `/opt/riscv32i`:
# Ubuntu packages needed: # Ubuntu packages needed:
@ -614,7 +620,7 @@ pure RV32I target, and install it in `/opt/riscv32i`:
git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
cd riscv-gnu-toolchain-rv32i cd riscv-gnu-toolchain-rv32i
git checkout 7e48594 git checkout 914224e
git submodule update --init --recursive git submodule update --init --recursive
mkdir build; cd build mkdir build; cd build
@ -643,7 +649,25 @@ By default calling any of those make targets will (re-)download the toolchain
sources. Run `make download-tools` to download the sources to `/var/cache/distfiles/` sources. Run `make download-tools` to download the sources to `/var/cache/distfiles/`
once in advance. once in advance.
*Note: This instructions are for git rev 7e48594 (2016-08-16) of riscv-gnu-toolchain.* *Note: This instructions are for git rev 914224e (2017-01-06) of riscv-gnu-toolchain.*
Linking binaries with newlib for PicoRV32
-----------------------------------------
The tool chains (see last section for install instructions) come with a version of
the newlib C standard library.
Use the linker script [firmware/riscv.ld](firmware/riscv.ld) for linking binaries
against the newlib library. Using this linker script will create a binary that
has its entry point at 0x10000. (The default linker script does not have a static
entry point, thus a proper ELF loader would be needed that can determine the
entry point at runtime while loading the program.)
Newlib comes with a few syscall stubs. You need to provide your own implementation
of those syscalls and link your program with this implementation, overwriting the
default stubs from newlib. See `syscalls.c` in [scripts/cxxdemo/](scripts/cxxdemo/)
for an example of how to do that.
Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs

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@ -51,7 +51,6 @@
#define regnum_t0 5 #define regnum_t0 5
#define regnum_t1 6 #define regnum_t1 6
#define regnum_t2 7 #define regnum_t2 7
#define regnum_fp 8 // x8 is s0 and also fp
#define regnum_s0 8 #define regnum_s0 8
#define regnum_s1 9 #define regnum_s1 9
#define regnum_a0 10 #define regnum_a0 10
@ -77,6 +76,9 @@
#define regnum_t5 30 #define regnum_t5 30
#define regnum_t6 31 #define regnum_t6 31
// x8 is s0 and also fp
#define regnum_fp 8
#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \ #define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0)) .word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))