mirror of https://github.com/YosysHQ/picorv32.git
Add newlib linker info to README file
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README.md
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README.md
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@ -23,6 +23,7 @@ PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wi
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- [Pico Co-Processor Interface (PCPI)](#pico-co-processor-interface-pcpi)
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- [Pico Co-Processor Interface (PCPI)](#pico-co-processor-interface-pcpi)
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- [Custom Instructions for IRQ Handling](#custom-instructions-for-irq-handling)
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- [Custom Instructions for IRQ Handling](#custom-instructions-for-irq-handling)
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- [Building a pure RV32I Toolchain](#building-a-pure-rv32i-toolchain)
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- [Building a pure RV32I Toolchain](#building-a-pure-rv32i-toolchain)
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- [Linking binaries with newlib for PicoRV32](#linking-binaries-with-newlib-for-picorv32)
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- [Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs](#evaluation-timing-and-utilization-on-xilinx-7-series-fpgas)
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- [Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs](#evaluation-timing-and-utilization-on-xilinx-7-series-fpgas)
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@ -596,13 +597,18 @@ Example:
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Building a pure RV32I Toolchain
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Building a pure RV32I Toolchain
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-------------------------------
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-------------------------------
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TL;DR: Run the following commands to build the complete toolchain:
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make download-tools
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make -j$(nproc) build-tools
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The default settings in the [riscv-tools](https://github.com/riscv/riscv-tools) build
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The default settings in the [riscv-tools](https://github.com/riscv/riscv-tools) build
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scripts will build a compiler, assembler and linker that can target any RISC-V ISA,
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scripts will build a compiler, assembler and linker that can target any RISC-V ISA,
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but the libraries are built for RV32G and RV64G targets. Follow the instructions
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but the libraries are built for RV32G and RV64G targets. Follow the instructions
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below to build a complete toolchain (including libraries) that target a pure RV32I
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below to build a complete toolchain (including libraries) that target a pure RV32I
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CPU.
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CPU.
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The following commands will build the RISC-V gnu toolchain and libraries for a
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The following commands will build the RISC-V GNU toolchain and libraries for a
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pure RV32I target, and install it in `/opt/riscv32i`:
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pure RV32I target, and install it in `/opt/riscv32i`:
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# Ubuntu packages needed:
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# Ubuntu packages needed:
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@ -614,7 +620,7 @@ pure RV32I target, and install it in `/opt/riscv32i`:
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git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
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git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
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cd riscv-gnu-toolchain-rv32i
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cd riscv-gnu-toolchain-rv32i
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git checkout 7e48594
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git checkout 914224e
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git submodule update --init --recursive
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git submodule update --init --recursive
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mkdir build; cd build
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mkdir build; cd build
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@ -643,7 +649,25 @@ By default calling any of those make targets will (re-)download the toolchain
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sources. Run `make download-tools` to download the sources to `/var/cache/distfiles/`
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sources. Run `make download-tools` to download the sources to `/var/cache/distfiles/`
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once in advance.
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once in advance.
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*Note: This instructions are for git rev 7e48594 (2016-08-16) of riscv-gnu-toolchain.*
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*Note: This instructions are for git rev 914224e (2017-01-06) of riscv-gnu-toolchain.*
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Linking binaries with newlib for PicoRV32
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-----------------------------------------
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The tool chains (see last section for install instructions) come with a version of
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the newlib C standard library.
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Use the linker script [firmware/riscv.ld](firmware/riscv.ld) for linking binaries
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against the newlib library. Using this linker script will create a binary that
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has its entry point at 0x10000. (The default linker script does not have a static
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entry point, thus a proper ELF loader would be needed that can determine the
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entry point at runtime while loading the program.)
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Newlib comes with a few syscall stubs. You need to provide your own implementation
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of those syscalls and link your program with this implementation, overwriting the
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default stubs from newlib. See `syscalls.c` in [scripts/cxxdemo/](scripts/cxxdemo/)
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for an example of how to do that.
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Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs
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Evaluation: Timing and Utilization on Xilinx 7-Series FPGAs
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@ -51,7 +51,6 @@
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#define regnum_t0 5
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#define regnum_t0 5
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#define regnum_t1 6
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#define regnum_t1 6
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#define regnum_t2 7
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#define regnum_t2 7
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#define regnum_fp 8 // x8 is s0 and also fp
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#define regnum_s0 8
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#define regnum_s0 8
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#define regnum_s1 9
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#define regnum_s1 9
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#define regnum_a0 10
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#define regnum_a0 10
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@ -77,6 +76,9 @@
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#define regnum_t5 30
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#define regnum_t5 30
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#define regnum_t6 31
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#define regnum_t6 31
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// x8 is s0 and also fp
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#define regnum_fp 8
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#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
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#define r_type_insn(_f7, _rs2, _rs1, _f3, _rd, _opc) \
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.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
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.word (((_f7) << 25) | ((_rs2) << 20) | ((_rs1) << 15) | ((_f3) << 12) | ((_rd) << 7) | ((_opc) << 0))
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