mirror of https://github.com/YosysHQ/picorv32.git
Some minor cleanups
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picorv32.v
20
picorv32.v
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@ -1168,9 +1168,11 @@ module picorv32 #(
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decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
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do_waitirq <= 0;
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if (ENABLE_TRACE)
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trace_valid <= 0;
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if (!ENABLE_TRACE)
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trace_data <= 'bx;
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if (!resetn) begin
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reg_pc <= PROGADDR_RESET;
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reg_next_pc <= PROGADDR_RESET;
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@ -1663,19 +1665,15 @@ module picorv32 #(
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// Formal Verification
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`ifdef FORMAL
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reg [3:0] cycle = 0;
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reg [3:0] last_mem_nowait;
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always @(posedge clk)
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if (~&cycle) cycle <= cycle + 1;
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reg [4:0] last_mem_ready;
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always @(posedge clk)
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last_mem_ready <= {last_mem_ready, mem_ready};
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restrict property (|last_mem_ready);
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last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
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restrict property (|last_mem_nowait || mem_ready || !mem_valid);
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reg ok;
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always @* begin
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restrict (resetn == |cycle);
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if (cycle) begin
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restrict (resetn == !$initstate);
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if (!$initstate) begin
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// instruction fetches are read-only
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if (mem_valid && mem_instr)
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assert (mem_wstrb == 0);
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@ -1685,7 +1683,7 @@ module picorv32 #(
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if (cpu_state == cpu_state_trap) ok = 1;
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if (cpu_state == cpu_state_fetch) ok = 1;
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if (cpu_state == cpu_state_ld_rs1) ok = 1;
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if (cpu_state == cpu_state_ld_rs2) ok = ENABLE_REGS_DUALPORT;
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if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
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if (cpu_state == cpu_state_exec) ok = 1;
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if (cpu_state == cpu_state_shift) ok = 1;
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if (cpu_state == cpu_state_stmem) ok = 1;
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