mirror of https://github.com/YosysHQ/picorv32.git
Added LATCHED_IRQ parameter
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10
README.md
10
README.md
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@ -176,6 +176,16 @@ Support for the timer is always disabled when ENABLE_IRQ is set to 0.
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A 1 bit in this bitmask corresponds to a permanently disabled IRQ.
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#### LATCHED_IRQ (default = 32'h ffff_ffff)
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A 1 bit in this bitmask indicates that the corresponding IRQ is "latched", i.e.
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when the IRQ line is high for only one cycle, the interrupt will be marked as
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pending and stay pending until the interrupt handler is called (aka "pulse
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interrupts" or "edge-triggered interrupts").
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Set a bit in this bitmask to 0 to convert an interrupt line to operate
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as "level sensitive" interrupt.
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#### PROGADDR_RESET (default = 32'h 0000_0000)
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The start address of the program.
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@ -36,6 +36,7 @@ module picorv32 #(
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parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
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parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
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parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
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parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
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parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
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parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010
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) (
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@ -579,7 +580,7 @@ module picorv32 #(
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if (ENABLE_COUNTERS)
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count_cycle <= resetn ? count_cycle + 1 : 0;
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next_irq_pending = irq_pending;
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next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
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if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
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if (timer - 1 == 0)
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@ -1148,6 +1149,7 @@ module picorv32_axi #(
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parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
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parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
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parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
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parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
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parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
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parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010
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) (
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@ -1239,6 +1241,7 @@ module picorv32_axi #(
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.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
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.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
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.MASKED_IRQ (MASKED_IRQ ),
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.LATCHED_IRQ (LATCHED_IRQ ),
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.PROGADDR_RESET (PROGADDR_RESET ),
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.PROGADDR_IRQ (PROGADDR_IRQ )
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) picorv32_core (
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