mirror of https://github.com/YosysHQ/picorv32.git
Merge branch 'master' into compressed
This commit is contained in:
commit
7909b2a7d9
14
Makefile
14
Makefile
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@ -27,24 +27,20 @@ check.smt2: picorv32.v
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test_sp: testbench_sp.exe firmware/firmware.hex
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vvp -N testbench_sp.exe
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test_axi: testbench_axi.exe firmware/firmware.hex
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vvp -N testbench_axi.exe
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test_axi: testbench.exe firmware/firmware.hex
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vvp -N testbench.exe +axi_test
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test_synth: testbench_synth.exe firmware/firmware.hex
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vvp -N testbench_synth.exe
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testbench.exe: testbench.v picorv32.v
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iverilog -o testbench.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) testbench.v picorv32.v
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iverilog -o testbench.exe $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) testbench.v picorv32.v
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chmod -x testbench.exe
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testbench_sp.exe: testbench.v picorv32.v
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iverilog -o testbench_sp.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) -DSP_TEST testbench.v picorv32.v
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iverilog -o testbench_sp.exe $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DSP_TEST testbench.v picorv32.v
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chmod -x testbench_sp.exe
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testbench_axi.exe: testbench.v picorv32.v
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iverilog -o testbench_axi.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) -DAXI_TEST testbench.v picorv32.v
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chmod -x testbench_axi.exe
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testbench_synth.exe: testbench.v synth.v
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iverilog -o testbench_synth.exe testbench.v synth.v
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chmod -x testbench_synth.exe
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@ -81,7 +77,7 @@ toc:
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clean:
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rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) check.smt2 check.vcd synth.v synth.log \
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firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
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testbench.exe testbench_sp.exe testbench_axi.exe testbench_synth.exe testbench.vcd
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testbench.exe testbench_sp.exe testbench_synth.exe testbench.vcd
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.PHONY: test view test_sp test_axi test_synth toc clean
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@ -299,7 +299,8 @@ that can run one memory transfer at a time:
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The core initiates a memory transfer by asserting `mem_valid`. The valid
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signal stays high until the peer asserts `mem_ready`. All core outputs
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are stable over the `mem_valid` period.
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are stable over the `mem_valid` period. If the memory transfer is an
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instruction fetch, the core asserts `mem_instr`.
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#### Read Transfer
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@ -318,6 +319,11 @@ In a write transfer `mem_wstrb` is not 0 and `mem_rdata` is unused. The memory
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write the data at `mem_wdata` to the address `mem_addr` and acknowledges the
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transfer by asserting `mem_ready`.
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The 4 bits of `mem_wstrb` are write enables for the four bytes in the addressed
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word. Only the 8 values `0000`, `1111`, `1100`, `0011`, `1000`, `0100`, `0010`,
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and `0001` are possible, i.e. no write, write 32 bits, write upper 16 bits,
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write lower 16, or write a single byte respectively.
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There is no need for an external wait cycle. The memory can acknowledge the
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write immediately with `mem_ready` going high in the same cycle as
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`mem_valid`, or `mem_ready` being tied to constant 1.
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188
testbench.v
188
testbench.v
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@ -6,20 +6,15 @@
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// means.
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`timescale 1 ns / 1 ps
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// `define VERBOSE
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module testbench;
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`ifndef VERILATOR
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module testbench #(
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parameter AXI_TEST = 0,
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parameter VERBOSE = 0
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);
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reg clk = 1;
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reg resetn = 0;
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reg [31:0] irq;
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wire trap;
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always @* begin
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irq = 0;
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irq[4] = &uut.picorv32_core.count_cycle[12:0];
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irq[5] = &uut.picorv32_core.count_cycle[15:0];
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end
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always #5 clk = ~clk;
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@ -28,27 +23,92 @@ module testbench;
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resetn <= 1;
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end
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initial begin
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if ($test$plusargs("vcd")) begin
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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end
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repeat (1000000) @(posedge clk);
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$display("TIMEOUT");
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$finish;
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end
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picorv32_wrapper #(
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.AXI_TEST (AXI_TEST),
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.VERBOSE (VERBOSE)
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) top (
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.clk (clk ),
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.resetn (resetn)
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);
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endmodule
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`endif
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module picorv32_wrapper #(
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parameter AXI_TEST = 0,
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parameter VERBOSE = 0
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) (
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input clk,
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input resetn
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);
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wire trap;
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reg [31:0] irq;
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always @* begin
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irq = 0;
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irq[4] = &uut.picorv32_core.count_cycle[12:0];
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irq[5] = &uut.picorv32_core.count_cycle[15:0];
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end
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wire mem_axi_awvalid;
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reg mem_axi_awready = 0;
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wire mem_axi_awready;
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wire [31:0] mem_axi_awaddr;
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wire [ 2:0] mem_axi_awprot;
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wire mem_axi_wvalid;
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reg mem_axi_wready = 0;
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wire mem_axi_wready;
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wire [31:0] mem_axi_wdata;
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wire [ 3:0] mem_axi_wstrb;
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reg mem_axi_bvalid = 0;
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wire mem_axi_bvalid;
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wire mem_axi_bready;
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wire mem_axi_arvalid;
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reg mem_axi_arready = 0;
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wire mem_axi_arready;
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wire [31:0] mem_axi_araddr;
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wire [ 2:0] mem_axi_arprot;
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reg mem_axi_rvalid = 0;
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wire mem_axi_rvalid;
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wire mem_axi_rready;
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reg [31:0] mem_axi_rdata;
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wire [31:0] mem_axi_rdata;
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axi4_memory #(
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.AXI_TEST (AXI_TEST),
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.VERBOSE (VERBOSE)
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) mem (
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.clk (clk ),
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.mem_axi_awvalid (mem_axi_awvalid ),
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.mem_axi_awready (mem_axi_awready ),
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.mem_axi_awaddr (mem_axi_awaddr ),
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.mem_axi_awprot (mem_axi_awprot ),
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.mem_axi_wvalid (mem_axi_wvalid ),
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.mem_axi_wready (mem_axi_wready ),
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.mem_axi_wdata (mem_axi_wdata ),
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.mem_axi_wstrb (mem_axi_wstrb ),
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.mem_axi_bvalid (mem_axi_bvalid ),
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.mem_axi_bready (mem_axi_bready ),
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.mem_axi_arvalid (mem_axi_arvalid ),
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.mem_axi_arready (mem_axi_arready ),
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.mem_axi_araddr (mem_axi_araddr ),
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.mem_axi_arprot (mem_axi_arprot ),
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.mem_axi_rvalid (mem_axi_rvalid ),
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.mem_axi_rready (mem_axi_rready ),
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.mem_axi_rdata (mem_axi_rdata )
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);
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picorv32_axi #(
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`ifdef SP_TEST
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@ -83,8 +143,60 @@ module testbench;
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.irq (irq )
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);
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reg [31:0] memory [0:64*1024/4-1];
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initial $readmemh("firmware/firmware.hex", memory);
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reg [1023:0] firmware_file;
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initial begin
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if(!$value$plusargs("firmware=%s", firmware_file))
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firmware_file = "firmware/firmware.hex";
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$readmemh(firmware_file, mem.memory);
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end
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integer cycle_counter;
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always @(posedge clk) begin
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cycle_counter <= resetn ? cycle_counter + 1 : 0;
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if (resetn && trap) begin
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`ifndef VERILATOR
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repeat (10) @(posedge clk);
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`endif
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$display("TRAP after %1d clock cycles", cycle_counter);
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$finish;
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end
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end
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endmodule
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module axi4_memory #(
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parameter AXI_TEST = 0,
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parameter VERBOSE = 0
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) (
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input clk,
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input mem_axi_awvalid,
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output reg mem_axi_awready = 0,
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input [31:0] mem_axi_awaddr,
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input [ 2:0] mem_axi_awprot,
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input mem_axi_wvalid,
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output reg mem_axi_wready = 0,
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input [31:0] mem_axi_wdata,
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input [ 3:0] mem_axi_wstrb,
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output reg mem_axi_bvalid = 0,
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input mem_axi_bready,
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input mem_axi_arvalid,
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output reg mem_axi_arready = 0,
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input [31:0] mem_axi_araddr,
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input [ 2:0] mem_axi_arprot,
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output mem_axi_rvalid = 0,
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input mem_axi_rready,
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output reg [31:0] mem_axi_rdata
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);
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reg [31:0] memory [0:64*1024/4-1] /* verilator public */;
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reg verbose;
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initial verbose = $test$plusargs("verbose") || VERBOSE;
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reg axi_test;
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initial axi_test = $test$plusargs("axi_test") || AXI_TEST;
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reg [63:0] xorshift64_state = 64'd88172645463325252;
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@ -101,12 +213,12 @@ module testbench;
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reg [4:0] async_axi_transaction = ~0;
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reg [4:0] delay_axi_transaction = 0;
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`ifdef AXI_TEST
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always @(posedge clk) begin
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if (axi_test) begin
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xorshift64_next;
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{fast_axi_transaction, async_axi_transaction, delay_axi_transaction} <= xorshift64_state;
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end
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`endif
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end
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reg latched_raddr_en = 0;
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reg latched_waddr_en = 0;
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@ -146,9 +258,8 @@ module testbench;
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end endtask
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task handle_axi_rvalid; begin
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`ifdef VERBOSE
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if(verbose)
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$display("RD: ADDR=%08x DATA=%08x%s", latched_raddr, memory[latched_raddr >> 2], latched_rinsn ? " INSN" : "");
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`endif
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if (latched_raddr < 64*1024) begin
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mem_axi_rdata <= memory[latched_raddr >> 2];
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mem_axi_rvalid <= 1;
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@ -160,9 +271,8 @@ module testbench;
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end endtask
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task handle_axi_bvalid; begin
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`ifdef VERBOSE
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if (verbose)
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$display("WR: ADDR=%08x DATA=%08x STRB=%04b", latched_waddr, latched_wdata, latched_wstrb);
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`endif
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if (latched_waddr < 64*1024) begin
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if (latched_wstrb[0]) memory[latched_waddr >> 2][ 7: 0] <= latched_wdata[ 7: 0];
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if (latched_wstrb[1]) memory[latched_waddr >> 2][15: 8] <= latched_wdata[15: 8];
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@ -170,15 +280,17 @@ module testbench;
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if (latched_wstrb[3]) memory[latched_waddr >> 2][31:24] <= latched_wdata[31:24];
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end else
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if (latched_waddr == 32'h1000_0000) begin
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`ifdef VERBOSE
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if (verbose) begin
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if (32 <= latched_wdata && latched_wdata < 128)
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$display("OUT: '%c'", latched_wdata);
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$display("OUT: '%c'", latched_wdata[7:0]);
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else
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$display("OUT: %3d", latched_wdata);
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`else
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$write("%c", latched_wdata);
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end else begin
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$write("%c", latched_wdata[7:0]);
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`ifndef VERILATOR
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$fflush();
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`endif
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end
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end else begin
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$display("OUT-OF-BOUNDS MEMORY WRITE TO %08x", latched_waddr);
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$finish;
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@ -237,24 +349,4 @@ module testbench;
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if (!mem_axi_rvalid && latched_raddr_en && !delay_axi_transaction[3]) handle_axi_rvalid;
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if (!mem_axi_bvalid && latched_waddr_en && latched_wdata_en && !delay_axi_transaction[4]) handle_axi_bvalid;
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end
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initial begin
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if ($test$plusargs("vcd")) begin
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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end
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repeat (1000000) @(posedge clk);
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$display("TIMEOUT");
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$finish;
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end
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integer cycle_counter;
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always @(posedge clk) begin
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cycle_counter <= resetn ? cycle_counter + 1 : 0;
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if (resetn && trap) begin
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repeat (10) @(posedge clk);
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$display("TRAP after %1d clock cycles", cycle_counter);
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$finish;
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end
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end
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endmodule
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