mirror of https://github.com/YosysHQ/picorv32.git
Added mul tests from riscv-tests
This commit is contained in:
Clifford Wolf
parent
dee66e136e
commit
7b17773bfc
6
Makefile
6
Makefile
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@ -31,7 +31,7 @@ firmware/firmware.bin: firmware/firmware.elf
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chmod -x $@
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firmware/firmware.elf: $(FIRMWARE_OBJS) $(TEST_OBJS) firmware/sections.lds
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riscv64-unknown-elf-gcc -Os -m32 -march=RV32I -ffreestanding -nostdlib -o $@ \
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riscv64-unknown-elf-gcc -Os -m32 -ffreestanding -nostdlib -o $@ \
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-Wl,-Bstatic,-T,firmware/sections.lds,-Map,firmware/firmware.map,--strip-debug \
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$(FIRMWARE_OBJS) $(TEST_OBJS) -lgcc
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chmod -x $@
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@ -40,10 +40,10 @@ firmware/start.o: firmware/start.S
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riscv64-unknown-elf-gcc -c -m32 -o $@ $<
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firmware/%.o: firmware/%.c
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riscv64-unknown-elf-gcc -c -Os -m32 -march=RV32I -ffreestanding -nostdlib -o $@ $<
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riscv64-unknown-elf-gcc -c -m32 -march=RV32I -Os -ffreestanding -nostdlib -o $@ $<
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tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
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riscv64-unknown-elf-gcc -m32 -march=RV32I -c -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
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riscv64-unknown-elf-gcc -c -m32 -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
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-DTEST_FUNC_TXT='"$(notdir $(basename $<))"' -DTEST_FUNC_RET=$(notdir $(basename $<))_ret $<
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clean:
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@ -217,6 +217,11 @@ start:
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TEST(or)
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TEST(and)
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TEST(mulh)
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TEST(mulhsu)
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TEST(mulhu)
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TEST(mul)
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TEST(simple)
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/* set stack pointer */
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@ -0,0 +1 @@
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Tests from https://github.com/riscv/riscv-tests/tree/master/isa/rv32ui
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@ -0,0 +1,84 @@
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# See LICENSE for license details.
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#*****************************************************************************
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# mul.S
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#-----------------------------------------------------------------------------
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#
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# Test mul instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 );
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TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 );
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TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 );
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TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 );
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TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 );
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TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 );
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TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 );
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TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 );
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TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d );
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TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab );
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TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 );
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TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff );
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TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 );
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TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff );
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#-------------------------------------------------------------
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# Source/Destination tests
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#-------------------------------------------------------------
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TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
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TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
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TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
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TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
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TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
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TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
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TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
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TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
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TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
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TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
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TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
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TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
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TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
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TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
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TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
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TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
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TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
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TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
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TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
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TEST_RR_ZEROSRC12( 28, mul, 0 );
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TEST_RR_ZERODEST( 29, mul, 33, 34 );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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@ -0,0 +1,81 @@
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# See LICENSE for license details.
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#*****************************************************************************
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# mulh.S
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#-----------------------------------------------------------------------------
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#
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# Test mulh instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 );
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TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 );
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TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 );
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TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 );
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TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 );
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TEST_RR_OP( 7, mulh, 0x00000000, 0x80000000, 0x00000000 );
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TEST_RR_OP(30, mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
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TEST_RR_OP(31, mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab );
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TEST_RR_OP(32, mulh, 0x00010000, 0xff000000, 0xff000000 );
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TEST_RR_OP(33, mulh, 0x00000000, 0xffffffff, 0xffffffff );
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TEST_RR_OP(34, mulh, 0xffffffff, 0xffffffff, 0x00000001 );
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TEST_RR_OP(35, mulh, 0xffffffff, 0x00000001, 0xffffffff );
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#-------------------------------------------------------------
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# Source/Destination tests
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#-------------------------------------------------------------
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TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 );
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 );
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TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 );
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TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 );
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TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 );
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TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 );
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TEST_RR_ZEROSRC12( 28, mulh, 0 );
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TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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@ -0,0 +1,83 @@
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# See LICENSE for license details.
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#*****************************************************************************
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# mulhsu.S
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#-----------------------------------------------------------------------------
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#
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# Test mulhsu instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
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TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
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TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
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TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
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TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 );
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TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
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TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
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TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
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TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 );
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TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
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TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
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TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff );
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#-------------------------------------------------------------
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# Source/Destination tests
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#-------------------------------------------------------------
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TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
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TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
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TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
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TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
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TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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@ -0,0 +1,82 @@
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# See LICENSE for license details.
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#*****************************************************************************
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# mulhu.S
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#-----------------------------------------------------------------------------
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#
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# Test mulhu instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 );
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TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 );
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TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 );
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TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 );
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TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 );
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TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 );
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TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d );
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TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
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TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 );
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TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff );
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TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 );
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TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff );
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#-------------------------------------------------------------
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# Source/Destination tests
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#-------------------------------------------------------------
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TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 );
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#-------------------------------------------------------------
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# Bypassing tests
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#-------------------------------------------------------------
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TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 );
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TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 );
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TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
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TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
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TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 );
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TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 );
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TEST_RR_ZEROSRC12( 28, mulhu, 0 );
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TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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