Hardware
/
picorv32
mirror of https://github.com/YosysHQ/picorv32.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Added misisng MUL_CLKGATE stage

This commit is contained in:
Clifford Wolf 2016-09-06 01:02:12 +02:00
parent 5fdee952c9
commit 7f946d0f84
1 changed files with 3 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
picorv32.v
View File

@ -1968,15 +1968,14 @@ module picorv32_pcpi_fast_mul #(
rs1_q <= rs1; rs1_q <= rs1;
rs2_q <= rs2; rs2_q <= rs2;
end end
if (!MUL_CLKGATE || active[1]) begin
rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
end
if (!MUL_CLKGATE || active[2]) begin if (!MUL_CLKGATE || active[2]) begin
rd_q <= rd; rd_q <= rd;
end end
end end
always @(posedge clk) begin
rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
end
always @(posedge clk) begin always @(posedge clk) begin
if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin
if (instr_rs1_signed) if (instr_rs1_signed)