mirror of https://github.com/YosysHQ/picorv32.git
More RVFI bugfixes
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25
picorv32.v
25
picorv32.v
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@ -1487,8 +1487,8 @@ module picorv32 #(
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
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`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
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reg_sh <= cpuregs_rs2;
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reg_sh <= cpuregs_rs2;
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reg_op2 <= cpuregs_rs2;
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reg_op2 <= cpuregs_rs2;
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dbg_rs2val <= cpuregs_rs1;
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dbg_rs2val <= cpuregs_rs2;
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dbg_rs2val_valid <= 0;
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dbg_rs2val_valid <= 1;
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if (pcpi_int_ready) begin
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if (pcpi_int_ready) begin
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mem_do_rinst <= 1;
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mem_do_rinst <= 1;
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pcpi_valid <= 0;
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pcpi_valid <= 0;
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@ -1625,7 +1625,7 @@ module picorv32 #(
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reg_sh <= cpuregs_rs2;
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reg_sh <= cpuregs_rs2;
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reg_op2 <= cpuregs_rs2;
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reg_op2 <= cpuregs_rs2;
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dbg_rs2val <= cpuregs_rs2;
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dbg_rs2val <= cpuregs_rs2;
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dbg_rs2val_valid <= 0;
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dbg_rs2val_valid <= 1;
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(* parallel_case *)
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(* parallel_case *)
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case (1'b1)
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case (1'b1)
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is_sb_sh_sw: begin
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is_sb_sh_sw: begin
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@ -1655,7 +1655,7 @@ module picorv32 #(
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reg_sh <= cpuregs_rs2;
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reg_sh <= cpuregs_rs2;
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reg_op2 <= cpuregs_rs2;
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reg_op2 <= cpuregs_rs2;
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dbg_rs2val <= cpuregs_rs2;
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dbg_rs2val <= cpuregs_rs2;
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dbg_rs2val_valid <= 0;
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dbg_rs2val_valid <= 1;
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(* parallel_case *)
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(* parallel_case *)
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case (1'b1)
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case (1'b1)
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@ -1864,15 +1864,26 @@ module picorv32 #(
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rvfi_valid <= resetn && launch_next_insn && dbg_valid_insn;
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rvfi_valid <= resetn && launch_next_insn && dbg_valid_insn;
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rvfi_opcode <= dbg_insn_opcode;
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rvfi_opcode <= dbg_insn_opcode;
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rvfi_rs1 <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
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rvfi_rs1 <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
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rvfi_rs2 <= dbg_rs1val_valid ? dbg_insn_rs2 : 0;
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rvfi_rs2 <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
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rvfi_pre_pc <= dbg_insn_addr;
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rvfi_pre_pc <= dbg_insn_addr;
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rvfi_pre_rs1 <= dbg_rs1val_valid ? dbg_rs1val : 0;
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rvfi_pre_rs1 <= dbg_rs1val_valid ? dbg_rs1val : 0;
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rvfi_pre_rs2 <= dbg_rs2val_valid ? dbg_rs2val : 0;
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rvfi_pre_rs2 <= dbg_rs2val_valid ? dbg_rs2val : 0;
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if (!resetn) begin
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rvfi_rd <= 0;
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rvfi_post_rd <= 0;
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end else
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if (cpuregs_write) begin
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rvfi_rd <= latched_rd;
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rvfi_post_rd <= latched_rd ? cpuregs_wrdata : 0;
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end else
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if (rvfi_valid) begin
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rvfi_rd <= 0;
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rvfi_post_rd <= 0;
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end
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end
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end
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always @* begin
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always @* begin
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rvfi_rd = cpuregs_write ? dbg_insn_rd : 0;
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rvfi_post_rd = rvfi_rd ? cpuregs_wrdata : 0;
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rvfi_post_pc = dbg_insn_addr;
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rvfi_post_pc = dbg_insn_addr;
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end
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end
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`endif
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`endif
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